Displaying 6 results from an estimated 6 matches for "hsdr".
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2017 Sep 20
0
Updating LLVM Tests for Patch
...pare
-mcpu=cortex-a53 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA
<%t %s
And the worst thing I witnessed was with the Hexagon back-end were my
changes in DAGCombiner trigger an Unreachable:
home/dev/llvm/build/./bin/llc -march=hexagon -mcpu=hexagonv5
-disable-hsdr <
/home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll |
/home/dev/llvm/build/./bin/FileCheck
/home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll
--
Exit Code: 2
Command Output (stderr):
--
ReplaceNodeResults not implemented for this target!
UNREACHABLE executed at
/h...
2017 Sep 20
3
Updating LLVM Tests for Patch
...>%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA
> <%t %s
>
> And the worst thing I witnessed was with the Hexagon back-end were my
> changes in DAGCombiner trigger an Unreachable:
>
> home/dev/llvm/build/./bin/llc -march=hexagon -mcpu=hexagonv5
> -disable-hsdr <
> /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll |
> /home/dev/llvm/build/./bin/FileCheck
> /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll
> --
> Exit Code: 2
>
> Command Output (stderr):
> --
> ReplaceNodeResults not implemented for...
2017 Sep 22
0
[Hexagon] Type Legalization
...mp;& FileCheck --check-prefix=CHECK-UseAA
> <%t %s
>
> And the worst thing I witnessed was with the Hexagon back-end were my
> changes in DAGCombiner trigger an Unreachable:
>
> home/dev/llvm/build/./bin/llc -march=hexagon -mcpu=hexagonv5
> -disable-hsdr <
> /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll |
> /home/dev/llvm/build/./bin/FileCheck
> /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll
> --
> Exit Code: 2
>
> Command Output (stderr):
> --
> Repla...
2017 Sep 22
2
[Hexagon] Type Legalization
...=CHECK-UseAA
> > <%t %s
> >
> > And the worst thing I witnessed was with the Hexagon back-end were my
> > changes in DAGCombiner trigger an Unreachable:
> >
> > home/dev/llvm/build/./bin/llc -march=hexagon -mcpu=hexagonv5
> > -disable-hsdr <
> > /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll |
> > /home/dev/llvm/build/./bin/FileCheck
> > /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll
> > --
> > Exit Code: 2
> >
> > Command Output (s...
2017 Sep 22
0
[Hexagon] Type Legalization
...t; >
> > And the worst thing I witnessed was with the Hexagon back-end
> were my
> > changes in DAGCombiner trigger an Unreachable:
> >
> > home/dev/llvm/build/./bin/llc -march=hexagon -mcpu=hexagonv5
> > -disable-hsdr <
> > /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll |
> > /home/dev/llvm/build/./bin/FileCheck
> > /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll
> > --
> > Exit Code: 2
> >
&...
2017 Sep 19
5
How to add optimizations to InstCombine correctly?
For the tests that are changing, you should see if those changes are
improvements, regressions, or neutral. This is unfortunately not always
obvious for x86 asm, so feel free to just post those diffs in an updated
version of the patch at D37896.
If the test files have auto-generated assertions (look for this string on
the first line of the test file: "NOTE: Assertions have been autogenerated