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2017 Dec 06
2
[AMDGPU] Strange results with different address spaces
> On Dec 6, 2017, at 02:28, Haidl, Michael <michael.haidl at uni-muenster.de> wrote:
>
> The IR goes through a backend agnostic preparation phase that brings it into SSA from and changes the AS from 0 to 1.
This sounds possibly problematic to me. The IR should be created with the correct address space to begin with. Changing this in the middle sounds suspect.
> After this