search for: hpet_id

...( !hpet_events ) return; - hpet_resume(); + hpet_resume(NULL); cfg = hpet_read32(HPET_CFG); @@ -704,10 +704,13 @@ int hpet_legacy_irq_tick(void) return 1; } +static u32 *hpet_boot_cfg; + u64 __init hpet_setup(void) { static u64 __initdata hpet_rate; u32 hpet_id, hpet_period; + unsigned int last; if ( hpet_rate ) return hpet_rate; @@ -732,7 +735,9 @@ u64 __init hpet_setup(void) return 0; } - hpet_resume(); + last = (hpet_id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT; + hpet_boot_cfg = xmalloc_array(u32,...

...ttr *); > extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg); > > -extern void native_compose_msi_msg(struct pci_dev *pdev, > +extern void native_compose_msi_msg(struct msi_irqs *msi, > unsigned int irq, unsigned int dest, > struct msi_msg *msg, u8 hpet_id); > extern void native_eoi_ioapic_pin(int apic, int pin, int vector); > diff --git a/arch/x86/include/asm/irq_remapping.h > b/arch/x86/include/asm/irq_remapping.h > index b7747c4..a10003d 100644 > --- a/arch/x86/include/asm/irq_remapping.h > +++ b/arch/x86/include/asm/irq_remappi...

...ttr *); > extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg); > > -extern void native_compose_msi_msg(struct pci_dev *pdev, > +extern void native_compose_msi_msg(struct msi_irqs *msi, > unsigned int irq, unsigned int dest, > struct msi_msg *msg, u8 hpet_id); > extern void native_eoi_ioapic_pin(int apic, int pin, int vector); > diff --git a/arch/x86/include/asm/irq_remapping.h > b/arch/x86/include/asm/irq_remapping.h > index b7747c4..a10003d 100644 > --- a/arch/x86/include/asm/irq_remapping.h > +++ b/arch/x86/include/asm/irq_remappi...

...struct io_apic_irq_attr *); extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg); -extern void native_compose_msi_msg(struct pci_dev *pdev, +extern void native_compose_msi_msg(struct msi_irqs *msi, unsigned int irq, unsigned int dest, struct msi_msg *msg, u8 hpet_id); extern void native_eoi_ioapic_pin(int apic, int pin, int vector); diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/irq_remapping.h index b7747c4..a10003d 100644 --- a/arch/x86/include/asm/irq_remapping.h +++ b/arch/x86/include/asm/irq_remapping.h @@ -47,7 +47,7 @@ extern...

...6/hpet.c Wed Nov 26 11:14:26 2008 +0000 +++ b/xen/arch/x86/hpet.c Wed Nov 26 19:22:03 2008 -0500 @@ -273,6 +273,8 @@ return hpet_rate; system_reset_latch = system_reset_counter; + if ( !hpet_address ) + return 0; set_fixmap_nocache(FIX_HPET_BASE, hpet_address); hpet_id = hpet_read32(HPET_ID); _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

...stion would be whether HPET legacy interrupts should be forced off in this case (rather than leaving whatever came from firmware). Signed-off-by: Jan Beulich <jbeulich@novell.com> --- a/xen/arch/x86/hpet.c +++ b/xen/arch/x86/hpet.c @@ -557,6 +557,9 @@ void hpet_broadcast_init(void) u32 hpet_id, cfg; int i; + if ( boot_cpu_has(X86_FEATURE_ARAT) ) + return; + if ( irq_channel == NULL ) { irq_channel = xmalloc_array(int, nr_irqs); _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensour...

Hi all, The series is a draft of generic MSI driver that supports PCI and Non-PCI device which have MSI capability. If you're not interested it, sorry for the noise. The series is based on Linux-3.16-rc1. MSI was introduced in PCI Spec 2.2. Currently, kernel MSI driver codes are bonding with PCI device. Because MSI has a lot advantages in design. More and more non-PCI devices want to use

Hi all, The series is a draft of generic MSI driver that supports PCI and Non-PCI device which have MSI capability. If you're not interested it, sorry for the noise. The series is based on Linux-3.16-rc1. MSI was introduced in PCI Spec 2.2. Currently, kernel MSI driver codes are bonding with PCI device. Because MSI has a lot advantages in design. More and more non-PCI devices want to use

1: IOMMU: properly check whether interrupt remapping is enabled 2: AMD IOMMU: only disable when certain IVRS consistency checks fail 3: VT-d: deal with 5500/5520/X58 errata Patch 1 and 2 are version 2 of a previously submitted, then withdrawn patch following up after XSA-36. Patch 3 is version 3 of a patch previously sent by Malcolm and Andrew. Signed-off-by: Jan Beulich

Hi Jan, After commit 2ca9fbd739b8a72b16dd790d0fff7b75f5488fb8 AMD IOMMU: allocate IRTE entries instead of using a static mapping, booting dom0 stalls several times. Sometimes this results in RCU stall warnings from the dom0 kernel, hitting the "any" key, on normal or serial console, makes the boot continue for a while but it stalls several times. (It also stalls on shutdown BTW) I have

Hi Ingo, Here''s the chunk of patches to add Xen Dom0 support (it''s probably worth creating a new xen/dom0 topic branch for it). A dom0 Xen domain is basically the same as a normal domU domain, but it has extra privileges to directly access hardware. There are two issues to deal with: - translating to and from the domain''s pseudo-physical addresses and real machine