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I'll comment from the perspective of someone that is in the Mesa, #dri-devel, #radeon channels myself and have watched their behaviour over the years. This is a real person that spams a load of information into a channel about their understanding of how hardware works. I have no idea what their goal is for spamming this information, could be some desire for acceptance from perceived smartness.

Is the channel now purposefully invite-only? If so, how is one supposed to join? Thanks, Stefan On Fri, Jun 26, 2020 at 12:23 PM Renato Golin via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On Fri, 26 Jun 2020 at 01:03, Ryan Houdek <sonicadvance1 at gmail.com> wrote: > > I'll comment from the perspective of someone that is in the Mesa, > #dri-devel, #radeon channels myself and have watched their behaviour over > the years. This is a real person that spams a load of information into a > channel about t...

I'm noticing limitations with tablegen and LLVM's handling of fixed length instruction encodings. It can only handle up to 64bit fixed length instruction encodings. I'm wondering if anyone has spent time investigating lifting this limitation and what all problems it would hit with various bits of LLVM assuming the max size is 64bit. In particular 128bit and 256bit fixed length