search for: hostbridg

Author: anish Repository: /hg/zfs-crypto/gate Revision: 7c4fe5bc3d340613b336f2b91002d33d0010a403 Log message: 6360419 get master aborts accessing config space of amd64 hostbridge devices on systems with CK8-04 device Files: update: usr/src/uts/i86pc/io/pci/pci.c update: usr/src/uts/i86pc/io/pci/pci_common.c update: usr/src/uts/i86pc/io/pci/pci_common.h update: usr/src/uts/i86pc/io/pci/pci_tools.c update: usr/src/uts/i86pc/io/pciex/npe.c

...rq deliver to. I'm reworking the msi_chip, and try to use msi_chip to eliminate all arch_msi_xxx() under every arch in kernel. And the important point is how to create the binding for the MSI device to the target msi_chip. For PCI device, some arm platform already bound the msi_chip to the pci hostbridge, then all pci devices under the pci hostbridge deliver their MSI irqs to the target msi_chip. And other platform create the binding in DTS file, then the MSI device can find their msi_chip by device_node. I don't know whether there are other situations, we should provide a generic interface th...

...rq deliver to. I'm reworking the msi_chip, and try to use msi_chip to eliminate all arch_msi_xxx() under every arch in kernel. And the important point is how to create the binding for the MSI device to the target msi_chip. For PCI device, some arm platform already bound the msi_chip to the pci hostbridge, then all pci devices under the pci hostbridge deliver their MSI irqs to the target msi_chip. And other platform create the binding in DTS file, then the MSI device can find their msi_chip by device_node. I don't know whether there are other situations, we should provide a generic interface th...

Certain combinations of hardware can't actually support the maximum detected speed. Add a quirk list that lists pairs of hostbridge/chip pci ids and the mode that they should work with. See https://bugs.freedesktop.org/show_bug.cgi?id=20341 Reported-by: Jason Detring <detringj at gmail.com> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- I didn't go as far as subdevice matching... IMO that's ove...

...dn't expect to change any PCI drivers, but only platform drivers that do native MSI, so we only have to change drivers that do not support any MSI at all yet and that need to be changed anyway in order to add support. > For PCI device, some arm platform already bound the msi_chip to the pci hostbridge, then all > pci devices under the pci hostbridge deliver their MSI irqs to the target msi_chip. > And other platform create the binding in DTS file, then the MSI device can find their msi_chip > by device_node. > I don't know whether there are other situations, we should provide a...

...e msi_chip, and try to use msi_chip to eliminate >> all arch_msi_xxx() under every arch in kernel. And the important point is how to create the >> binding for the MSI device to the target msi_chip. >> >> For PCI device, some arm platform already bound the msi_chip to the pci hostbridge, then all >> pci devices under the pci hostbridge deliver their MSI irqs to the target msi_chip. >> And other platform create the binding in DTS file, then the MSI device can find their msi_chip >> by device_node. >> I don't know whether there are other situations, we s...

...;m reworking the msi_chip, and try to use msi_chip to eliminate > all arch_msi_xxx() under every arch in kernel. And the important point is how to create the > binding for the MSI device to the target msi_chip. > > For PCI device, some arm platform already bound the msi_chip to the pci hostbridge, then all > pci devices under the pci hostbridge deliver their MSI irqs to the target msi_chip. > And other platform create the binding in DTS file, then the MSI device can find their msi_chip > by device_node. > I don't know whether there are other situations, we should provide a...

...;m reworking the msi_chip, and try to use msi_chip to eliminate > all arch_msi_xxx() under every arch in kernel. And the important point is how to create the > binding for the MSI device to the target msi_chip. > > For PCI device, some arm platform already bound the msi_chip to the pci hostbridge, then all > pci devices under the pci hostbridge deliver their MSI irqs to the target msi_chip. > And other platform create the binding in DTS file, then the MSI device can find their msi_chip > by device_node. > I don't know whether there are other situations, we should provide a...

...8f91ded399aa52be0424cd76 Log message: 6390254 fpc shouldn''t clutter sun4v unix with specialized hypervisor definitions 6390258 fpc should use hypervisor versioning APIs when available 6393704 pcitool dumps core with invalid options 6396857 fpc module causes boot-time panic on non-fire pcie hostbridge 6402441 sun4v px driver needs to verify diag group access with hypervisor for pcitool 6402456 Move all VPCI hypervisor defs out of hypervisor_api.h into a px header file 6404203 Use hypervisor versioning for better checking of suitable fire perf counter platforms Files: update: usr/src/uts/sun4/...

Adam Jackson (3): Death to RCS tags. Fix distcheck sis 0.10.0 Dave Airlie (11): inital SiS pci access patch fix warnings in build fix thinko between open/fopen another open/fopen confusion fixup type punning convert all hostbridge read/writes to accessor functions finish off read/write long conversion switch bios reading over use map domain memory with pciinfo fixup unmap memory fix some thinkos in the pciaccess patch, this now works on real hardware Julien Cristau (2): Require pciaccess...

On 10/27/2013 09:54 AM, Ilia Mirkin wrote: > Certain combinations of hardware can't actually support the maximum > detected speed. Add a quirk list that lists pairs of hostbridge/chip pci > ids and the mode that they should work with. > > See https://bugs.freedesktop.org/show_bug.cgi?id=20341 It seems like this quirk is likely too specific. This almost certainly affects more than 5600 Ultra cards and probably not just NV cards either. It probably affects more V...

My setup: A SuperMicro 24-drive chassis with Intel dual-processor motherboard, three LSI SAS3081E controllers, and 24 SATA 2TB hard drives, divided into three pools with each pool a single eight-disk RAID-Z2. (Boot is an SSD connected to motherboard SATA.) This morning I got a cheerful email from my monitoring script: "Zchecker has discovered a problem on bigdawg." The full output is

...mcblk0 init=/bin/bash rw ip=dhcp"; This is how I launch the model ( where the variables of course contain the right paths ): ./model_shell ../resources/Cortex-A15x1/cadi_system_Linux-Release-GCC-4.4.so $1 -C motherboard.flashloader0.fname=$2 -C motherboard.smsc_91c111.enabled=1 -C motherboard.hostbridge.userNetworking=1 -C motherboard.pl011_uart0.out_file=./log.txt -C motherboard.mmc.p_mmc_file="$3" To get a basic filesystem I: - created a empty file ( with fallocate or dd ) - formated it ext4 - mounted the file and used HOSTNAME=armhf sudo debootstrap --foreign --arch armhf wheezy $pa...

...m device drivers, because we can find the target msi_chip by some platform interfaces(like the existing of_pci_find_msi_chip_by_node()). So we no need to explicitly provide the msi_chip as the function argument. > >> For PCI device, some arm platform already bound the msi_chip to the pci hostbridge, then all >> pci devices under the pci hostbridge deliver their MSI irqs to the target msi_chip. >> And other platform create the binding in DTS file, then the MSI device can find their msi_chip >> by device_node. >> I don't know whether there are other situations, we s...

...m device drivers, because we can find the target msi_chip by some platform interfaces(like the existing of_pci_find_msi_chip_by_node()). So we no need to explicitly provide the msi_chip as the function argument. > >> For PCI device, some arm platform already bound the msi_chip to the pci hostbridge, then all >> pci devices under the pci hostbridge deliver their MSI irqs to the target msi_chip. >> And other platform create the binding in DTS file, then the MSI device can find their msi_chip >> by device_node. >> I don't know whether there are other situations, we s...

Hi all, The series is a draft of generic MSI driver that supports PCI and Non-PCI device which have MSI capability. If you're not interested it, sorry for the noise. The series is based on Linux-3.16-rc1. MSI was introduced in PCI Spec 2.2. Currently, kernel MSI driver codes are bonding with PCI device. Because MSI has a lot advantages in design. More and more non-PCI devices want to use

Hi all, The series is a draft of generic MSI driver that supports PCI and Non-PCI device which have MSI capability. If you're not interested it, sorry for the noise. The series is based on Linux-3.16-rc1. MSI was introduced in PCI Spec 2.2. Currently, kernel MSI driver codes are bonding with PCI device. Because MSI has a lot advantages in design. More and more non-PCI devices want to use