search for: hoseini

Yes, I have done exactly the same. The wawanalyzer is the same. I changed ARM.h and ARMTargetMachine.cpp in the tager/arm folder. then I make tool/llc and lib folder. On Tue, Nov 17, 2015 at 10:55 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/17/15 12:16 AM, fateme Hoseini via llvm-dev wrote: > > Hi, > So, I run my pass in X86 target with llc command and it printed out > "hello****". Now I am trying to do the same pass for ARM target. So I did > exactly what I did for X86 as mentioned in my previous posts. When I run > the following comman...

Hi, Is there a way to get instruction's offset at compile time with llvm for ARM? I am trying to create a map between instructions at compile time and this run-time info. Since PC is a relative value, I am trying to use the instruction's offset as a constant property of instruction to create this map. I think offset information should be available to create the executable, if so where to

...: llc -march=arm test.ll -o test nothing prints out. I did the same for MIPS target too and I got no result. Can anyone tell me what I'm doing wrong. Is there any difference between writing machinefunction passes in x86 and other targets? Thank you, Fami On Fri, Nov 6, 2015 at 10:56 AM, fateme Hoseini <hoseini.f at gmail.com> wrote: > Hi > So I m trying to write my first backend pass. I created a file in > target\x86\wawanalyzer.cpp based on hexagonHardwareLoops.cpp file. Now it's > just a simple file that prints hello to the output. I have attached the > file to this p...

Thank you so much. That helped alot. Fami On Wed, Nov 4, 2015 at 9:40 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/3/15 7:54 PM, fateme Hoseini wrote: > > Dear John, > Thank you so much for your help. I looked at those documents. Could you > kindly answer the following questions: > > Does it mean that I have to make my own backend target in order to write a > machine pass even if I want to run a simple machinefunction...

.... Could you please help me on how to convert these physical register number to the ARM related register? I mean the 15 GPRs in ARM. Thank you, Fami On Sat, Dec 19, 2015 at 5:02 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Fami, > > On 19 December 2015 at 11:34, fateme Hoseini via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > I get my machine instruction, but I don't know how to get dest reg. I > looked > > at MachineInstr.h but couldn't find it out. > > You probably want to iterate through the instruction's operands > (M...

Hello everyone, I am trying to add checkpoints to my IR code. In order to do that I need to add this instruction: call void @m5_checkpoint(i64 0, i64 0) to some of the basic blocks in my benchmark. m5_checkpoint is a function defined for checkpointing in another simulator and is not included in my benchmark source code. So I need to create this instruction and I couldn't figure out how to do

.... > > Regarding documentation, have you looked at the following? > > http://llvm.org/docs/WritingAnLLVMBackend.html > http://llvm.org/docs/CodeGenerator.html > http://llvm.org/docs/MIRLangRef.html > > Regards, > > John Criswell > > > On 11/3/15 3:47 PM, fateme Hoseini via llvm-dev wrote: > > Hi everyone, > I am a LLVM newbie. I need to write a machinefunction pass for my project. > This should be an analyzer of the machine code to do some profiling. I have > written a couple of function passes for front end, but it seems they are > completely d...

Hi Does LLVM dynamically run the program to obtain profiling information like branch weight? if so, can we access the information regarding this run like the number of instructions that have been executed dynamically between two specific points of the program? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hello everyone, I am trying to write a code to do the following: 1. Get an ARM machine instruction 2. Find destination register of that instruction that has been written 3. set a bit in a vector, according to that register number. (Since it's ARM, I have a 15 bit vector) It means if I have : add r0, r1, r0 I want to get r0 as dest reg and set the index 0 of my vector to 1. I get my machine

Hi, Is it possible to add a spill code (a pair of store /load ) to the machinecode in a pass before the instruction emitter? If so, how can I calculate the address (offset to the sp) for the spill store/load instructions? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi everyone, I am a new commer and I 'm tying to use LLVM to cross compile a code. I want to cross compile to MIPS and the host is the default x86. The more I read the document the more confused I get. I see documents on cross-compiling to ARM. But some install some gcc packages, while some use clang. I don't know where to start and how to do it. Is this just enough to run a command line

Hi everyone, I am a LLVM newbie. I need to write a machinefunction pass for my project. This should be an analyzer of the machine code to do some profiling. I have written a couple of function passes for front end, but it seems they are completely different. I searched through forum and llvm documents, but couldn't find anything useful or questions were unanswered. Can anyone reference me to

Hello everyone, As I mentioned in my previous posts,I am using a machinefunction pass to find all the loops in the program and do some analysis on them. I have completed my pass now and it works correctly. but the only issue is that,I have noticed that if I have two functions in my program, and one of them is part of the loop for another one ,by using runonmachinefunction(), I will get one loop

Ryan Taylor via llvm-dev <llvm-dev at lists.llvm.org> writes: > r0 gets overwritten inside the loop (assuming dst, src, src), is ldr > r0, [r5] needed to initialize r0 for the loop at each iteration? Register allocation should handle that if the load is hoisted. I'm with the others. The printf is the most likely culprit. -0David > On Thu, Mar 28, 2019