Displaying 3 results from an estimated 3 matches for "hoogerbrugg".
Did you mean:
hoogerbrugge
2014 Jul 17
3
[LLVMdev] Preventing IR instruction duplication
Hi,
For a certain type of analysis I generate inline assembly which I insert
into the LLVM IR code. This
inline assembly code contains labels that should not be duplicated. Problem
is that the tail
duplication pass duplicates code. It checks isNotDuplicatable on a machine
instruction however
there is no such a flag on an IR instruction that I could set. Is there a
way to tell in an IR pass
that
2013 Oct 11
3
[LLVMdev] Generate code for ARM Cortex m0, m3, and m4.
Hi,
I am trying to cross compile code for ARM Cortex m0, m3, and m4.
For m0, I use:
-target armv6--eabi -mcpu=cortex-m0
That seems to work. For m3 and m4, I use the following which does not work
(fatal error: error in backend: CPU: 'cortex-m3' does not support ARM mode):
-target armv7m--eabi -mcpu=cortex-m3
and
-target armv7em--eabi -mcpu=cortex-m4
Who can help me with the
2013 Oct 12
0
[LLVMdev] Generate code for ARM Cortex m0, m3, and m4.
Hi Jan,
For Cortex-M0, you should probably use the armv6m string in the target
triple. For M3 and M4 you need to use the thumbv7m arch string, -mthumb
won't be necessary.
Amara
On 11 October 2013 19:23, Jan Hoogerbrugge <
jan.hoogerbrugge at biface-tools.com> wrote:
> Hi,
>
> I am trying to cross compile code for ARM Cortex m0, m3, and m4.
>
> For m0, I use:
>
> -target armv6--eabi -mcpu=cortex-m0
>
> That seems to work. For m3 and m4, I use the following which does not work
&g...