search for: hongjiu

...nt: Wednesday, August 19, 2020 12:52 PM To: Kaylor, Andrew <andrew.kaylor at intel.com>; Luo, Yuanke <yuanke.luo at intel.com>; Philip Reames <listmail at philipreames.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Topper, Craig <craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. On 8/19/20 10:24 AM, Kaylor, Andrew wrote: > When the tile shape is unknown at compile time, how do you plan to do the register allocation of the tiles? My question is: do you do the allocation fo...

...2020 12:35 PM > *To:* Topper, Craig <craig.topper at intel.com>; Kaylor, Andrew > <andrew.kaylor at intel.com>; Luo, Yuanke <yuanke.luo at intel.com>; Philip > Reames <listmail at philipreames.com>; llvm-dev at lists.llvm.org; > florian_hahn at apple.com; Lu, Hongjiu <hongjiu.lu at intel.com> > *Subject:* Re: [llvm-dev] Intel AMX programming model discussion. > > On 8/19/20 3:09 PM, Topper, Craig wrote: > > The width and height can be runtime values that we would just copy > into 64 byte configuration block we pass to ldtilecfg....

...ent: Wednesday, August 19, 2020 5:14 AM To: Luo, Yuanke <yuanke.luo at intel.com>; Kaylor, Andrew <andrew.kaylor at intel.com>; Philip Reames <listmail at philipreames.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Topper, Craig <craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. On 8/19/20 5:34 AM, Luo, Yuanke wrote: There is no problem to have 256 register classes. Just a lot of register classes to me. We don't assume the shape of each physical register be 16x16, it is d...

...; Sent: Friday, August 21, 2020 3:35 AM To: Topper, Craig <craig.topper at intel.com>; Kaylor, Andrew <andrew.kaylor at intel.com>; Luo, Yuanke <yuanke.luo at intel.com>; Philip Reames <listmail at philipreames.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. On 8/19/20 3:09 PM, Topper, Craig wrote: The width and height can be runtime values that we would just copy into 64 byte configuration block we pass to ldtilecfg. So the code doesn't need to be mu...

...: Friday, September 4, 2020 9:47 PM To: 'Hal Finkel' <hfinkel at anl.gov>; Topper, Craig <craig.topper at intel.com>; Kaylor, Andrew <andrew.kaylor at intel.com>; Philip Reames <listmail at philipreames.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: RE: [llvm-dev] Intel AMX programming model discussion. Hi Hal, Generally, your proposal to adapt tile RA to Greedy RA looks good to me. Thank you! I plan to do some prototype for the proposal. Since there is 3 RA in LLVM infrastructure, we need 3 schemes to...

...ent: Wednesday, August 19, 2020 4:58 PM To: Luo, Yuanke <yuanke.luo at intel.com>; Kaylor, Andrew <andrew.kaylor at intel.com>; Philip Reames <listmail at philipreames.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Topper, Craig <craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. On 8/19/20 2:21 AM, Luo, Yuanke wrote: Hi Hal, There is 3 aspect to be solved. 1. The HW support max shape 16x16, so there are many register classes from 1x1 to 16x16. We need 256 register cla...

On 7 June 2016 at 10:54, Shi, Steven <steven.shi at intel.com> wrote: > Hi Rafael, > I finally enable the clang LTO build with small code model and PIE, and my clang LTO Uefi firmware works now. Thank you! But I have one more issue on the clang normal build (without LTO) now. I find the small code model + "-fpie" build option will let clang generate some R_X86_64_GOTPCREL

..., 2020 5:03 PM > *To:* Luo, Yuanke <yuanke.luo at intel.com>; Topper, Craig > <craig.topper at intel.com>; Kaylor, Andrew <andrew.kaylor at intel.com>; > Philip Reames <listmail at philipreames.com>; llvm-dev at lists.llvm.org; > florian_hahn at apple.com; Lu, Hongjiu <hongjiu.lu at intel.com> > *Subject:* Re: [llvm-dev] Intel AMX programming model discussion. > > Hi, Yuanke, > > Thanks for writing this up. Let me back up a bit because the scheme I > proposed last week doesn't work without further modification: within a > particu...

...ent: Wednesday, August 19, 2020 8:20 AM To: Kaylor, Andrew <andrew.kaylor at intel.com>; Philip Reames <listmail at philipreames.com>; Luo, Yuanke <yuanke.luo at intel.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Topper, Craig <craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. Hi, Andy, I don't quite understand everything that's going on here. Could we model this as: 1. Define a collection of register classes, one for 2x4 tiles, one for 4x2 tiles, etc. each popula...

From: Hal Finkel <hfinkel at anl.gov> Sent: Friday, August 14, 2020 11:27 PM To: Luo, Yuanke <yuanke.luo at intel.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Kaylor, Andrew <andrew.kaylor at intel.com>; Topper, Craig <craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. On 8/14/20 8:27 AM, Luo, Yuanke via llvm-dev wrote: Hi, Intel Advanced Matrix Extensions (Intel AMX) is a new programming paradigm consisting of two components: a set of 2-dimensional registers (tiles...

...m: Philip Reames <listmail at philipreames.com> Sent: Friday, August 14, 2020 8:29 PM To: Luo, Yuanke <yuanke.luo at intel.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Kaylor, Andrew <andrew.kaylor at intel.com>; Topper, Craig <craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. I find your answer unconvincing. I'm not going to debate it as I don't wish to take the time to build the appropriate context, but my initial response is skepticism. Philip On 8/14/20 4:49 PM...

...ust 21, 2020 2:12 PM > *To:* Hal Finkel <hfinkel at anl.gov>; Topper, Craig > <craig.topper at intel.com>; Kaylor, Andrew <andrew.kaylor at intel.com>; > Philip Reames <listmail at philipreames.com>; llvm-dev at lists.llvm.org; > florian_hahn at apple.com; Lu, Hongjiu <hongjiu.lu at intel.com> > *Subject:* RE: [llvm-dev] Intel AMX programming model discussion. > > Hi Hal, > > The proposal is attractive to me, but there is something I still can’t > figure out. Let’s take below MIR as an example. We assume we have 256 > register classe...

...Philip Reames <listmail at philipreames.com> Sent: Saturday, August 15, 2020 11:29 AM To: Luo, Yuanke <yuanke.luo at intel.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Kaylor, Andrew <andrew.kaylor at intel.com>; Topper, Craig <craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. I find your answer unconvincing. I'm not going to debate it as I don't wish to take the time to build the appropriate context, but my initial response is skepticism. Philip On 8/14/20 4:49 PM...

...Philip Reames <listmail at philipreames.com> Sent: Saturday, August 15, 2020 1:17 AM To: Luo, Yuanke <yuanke.luo at intel.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Kaylor, Andrew <andrew.kaylor at intel.com>; Topper, Craig <craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. On 8/14/20 6:27 AM, Luo, Yuanke via llvm-dev wrote: Hi, Intel Advanced Matrix Extensions (Intel AMX) is a new programming paradigm consisting of two components: a set of 2-dimensional registers (tiles...

...39;m a little crushed. John. > > Sjoerd. > > ________________________________ > From: llvm-dev <llvm-dev-bounces at lists.llvm.org> on behalf of Kaylor, > Andrew via llvm-dev <llvm-dev at lists.llvm.org> > Sent: 24 January 2019 00:23 > To: Ahmed Bougacha; Lu, Hongjiu > Cc: llvm-dev; cfe-dev at lists.llvm.org > Subject: Re: [llvm-dev] [cfe-dev] _Float16 support > > It seems that there are several issues here: > > 1. Should the front end be concerned with whether or not the IR that > it is emitting can be translated into a well-defined IR? &...

Hi, Intel Advanced Matrix Extensions (Intel AMX) is a new programming paradigm consisting of two components: a set of 2-dimensional registers (tiles) representing sub-arrays from a larger 2-dimensional memory image, and accelerators able to operate on tiles. Capability of Intel AMX implementation is enumerated by palettes. Two palettes are supported: palette 0 represents the initialized state and

It seems that there are several issues here: 1. Should the front end be concerned with whether or not the IR that it is emitting can be translated into a well-defined IR? 2. How should the selection DAG handle data types whose representation isn't defined by the ABI we're targeting? 3. What should the ABI do with half-precision floats? Working backward... The third question here is