Displaying 3 results from an estimated 3 matches for "hl16".
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hi16
2012 Apr 25
2
[LLVMdev] LLVM Backend for Z80. ADD -> replaced -> OR
...rk, but for second assigned :OR with 2" will not work.
I suspect that llc is assuming that HL will contain 8 (that's the start) and
or-ing 8 with 1 or with 2 is ok.
But my HL has also added SP to it.
This is how my ISD::FrameIndex instruction look like:
def addHLdisp : Z80Instr<(outs HL16:$dst), (ins i16imm:$disp, GPR16:$src),
"ld $dst, $disp\n\tadd $dst,$src",
[(set HL16:$dst, (add GPR16:$src, (i16 imm:$disp)))]>;
So it say that HL16:$dst wich is only HL register, will be changed.
I also tried to change it to
<(outs HL16:$dst), (ins i16imm:$disp, SP16:$src),
But...
2012 Apr 25
0
[LLVMdev] LLVM Backend for Z80. ADD -> replaced -> OR
...2" will not
> work.
>
> I suspect that llc is assuming that HL will contain 8 (that's the start)
> and or-ing 8 with 1 or with 2 is ok.
> But my HL has also added SP to it.
> This is how my ISD::FrameIndex instruction look like:
>
> def addHLdisp : Z80Instr<(outs HL16:$dst), (ins i16imm:$disp, GPR16:$src),
> "ld $dst, $disp\n\tadd $dst,$src",
> [(set HL16:$dst, (add GPR16:$src, (i16 imm:$disp)))]>;
>
> So it say that HL16:$dst wich is only HL register, will be changed.
> I also tried to change it to
> <(outs HL16:$dst), (ins i16...
2012 Apr 25
1
[LLVMdev] LLVM Backend for Z80. ADD -> replaced -> OR
...>>
>> I suspect that llc is assuming that HL will contain 8 (that's the start)
>> and or-ing 8 with 1 or with 2 is ok.
>> But my HL has also added SP to it.
>> This is how my ISD::FrameIndex instruction look like:
>>
>> def addHLdisp : Z80Instr<(outs HL16:$dst), (ins i16imm:$disp, GPR16:$src),
>> "ld $dst, $disp\n\tadd $dst,$src",
>> [(set HL16:$dst, (add GPR16:$src, (i16 imm:$disp)))]>;
>>
>> So it say that HL16:$dst wich is only HL register, will be changed.
>> I also tried to change it to
>> <(o...