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Dan Gohman wrote: > There certainly are wishlist items for TableGen and TableGen-based > instruction descriptions, though I don't know of an official list. > Offhand, > a few things that come to mind are the ability to handle nodes with > multiple results, Is there an official workaround, BTW? - Volodya

...which use two neighboring regs at once, which i'm trying to employ using virtual regs with subs. For example, it I want to move one 64-bit virtual reg to another, I'm trying to use the following pattern: def LoReg: OutPatFrag<(ops node:$Rd), (EXTRACT_SUBREG (i64 $Rd), isub_lo)>; def HiReg: OutPatFrag<(ops node:$Rd), (EXTRACT_SUBREG (i64 $Rd), isub_hi)>; def MOVi64rr : Pat<(set GPR64:$Rd, GPR64:$Rn), (REG_SEQUENCE GPR64, (MOVi32rr (HiReg GPR64:$Rn)), isub_hi, (MOVi32rr (LoReg GPR64:$Rn)), isub_lo)>; isub_hi and isub_lo are subregs of a single 64-bit v...

...dded and merged into R15. Here is my selectionDAG code, i used X86's MUL code and adapted it to my target: case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { SDValue Op1 = N->getOperand(0); SDValue Op2 = N->getOperand(1); unsigned LoReg = R0, HiReg = R1; unsigned Opc = MULRdRr; SDValue InFlag = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag,...

On Sep 9, 2010, at 12:59 PM, Borja Ferrer wrote: > Hello, i've noticed a new possible missed optimization while testing more trivial code. > This time it's not a with a xor but with a multiplication instruction and the example is little bit more involved. > > C code: > > typedef short t; > t foo(t a, t b) > { > t a4 = a*b; > return a4; > } >

Hello, i've noticed a new possible missed optimization while testing more trivial code. This time it's not a with a xor but with a multiplication instruction and the example is little bit more involved. C code: typedef short t; t foo(t a, t b) { t a4 = a*b; return a4; } argument "a" is passed in R15:R14, argument "b" in R13:R12, the return value is stored in