Displaying 20 results from an estimated 40 matches for "highlevel".
2012 Apr 05
1
[LLVMdev] splat instruction
Hi!
as highlevel languages (like opencl) support operations with a vector
on one side and a scalar on the other side (e.g. vector * scalar) it would
be convenient if llvm ir would have a splat instruction that takes
a scalar and produces a vector with all elements filled with the scalar.
i assume that i'm not...
2013 Dec 03
2
[LLVMdev] Newbie question: LLVM IR, printf, and varargs
...@printf(i8* getelementptr inbounds ([11 x
i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([5 x i8]* @.str1,
i32 0, i32 0)) nounwind
ret i32 0
}
declare i32 @printf(i8* nocapture readonly, ...) nounwind
A good thing about this question is that the answer will find its way into
the Mapping Highlevel doc, which is why I am asking it in the first place.
This is on Windows using a 32-bit version of LLVM llc v3.4 (built about a
week ago).
I searched the LR, the FAQ, and Google but found nothing of relevance.
-- Mikael
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2011 Dec 28
3
[LLVMdev] InstCombine "pessimizes" trunc i8 to i1?
...ansformation is exposing it to the optimizer.
>
> Why do you consider this to be a pessimization? Does one produce inferior machine code?
I consider it a pessimization as it is one additional instruction and
I'm mainly interested in target
independent optimizations because I regenerate highlevel code from it
("Exporting 3D scenes from Maya to WebGL using clang and llvm").
For example from the given code before the transformation I can easily
regenerate
myGlobal ? 1.0f : -1.0f
while after the transformation I get
(myGlobal & 1) != 0 ? 1.0f : -1.0f
which is not good for shadin...
2007 Dec 19
1
[LLVMdev] Conditional Predicate Extraction
...iables (llvm specific), in order to maintain consistent behaviour when
using this information with anyother simulator, it would be better if these
predicates have syntax very similar (or exactly) as that of the high level
language.
The questions are:
1. Is it possible to somehow intersperse IR and highlevel code of the
program (in C or C++).
2. Is it possible to incorporate some optimizations using llvm-gcc to make
the generated IR very close to the high level language, without affecting
the branch information.
Suggestions and answers are welcome.
Regards
Prabhat
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2003 Dec 07
2
par(las = 1) not possible in polymap(), library(splancs)?
Dear all,
I want my PhD thesis which I hand in tomorrow to look even nicer:
Does polymap in the splancs library not allow horizontal plotting of
y-labels? I have tried
polymap(studyarea, xlab = "x (m)", ylab = "y (m)", las = 1)
but it doesn't change the labels?
Mayby some function in library(spatstat) support las?
Thanks!
Sincerely,
Tord
2013 Dec 03
2
[LLVMdev] Newbie question: LLVM IR, printf, and varargs
...8* getelementptr inbounds ([5 x i8]* @.str1,
>> i32 0, i32 0)) nounwind
>> ret i32 0
>> }
>>
>> declare i32 @printf(i8* nocapture readonly, ...) nounwind
>>
>> A good thing about this question is that the answer will find its way
>> into the Mapping Highlevel doc, which is why I am asking it in the first
>> place.
>>
>> This is on Windows using a 32-bit version of LLVM llc v3.4 (built about a
>> week ago).
>>
>> I searched the LR, the FAQ, and Google but found nothing of relevance.
>>
>>
> You're mi...
2006 Dec 05
2
intro + specification remarks + some questions
...- decode codebooks
- decode floors
- decode residues
- decode mappings
- decode modes
- read (packets) as audio packet:
- header
- 'packet decode' floor curves
- 'packet decode' residues
- synthesise
I.e. a bit more highlevel structure to the docs would be cool and
provide a lot of clarity. The lowlevel pseudocode is great and highly
readable, but I did notice that somewhere halfway (after decoding the
headers) the style changed quite a bit leading me to suspect two authors
at work.
* The second part (packet decode...
2010 Sep 03
0
[LLVMdev] Thoughts about the llvm architecture -
...ne (on llvm ir)
llvm ir -> selection dag
lower
combine
legalize
combine
...
I wonder if there is duplicate code in instCombine (on llvm ir, e.g.
llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp)
and combine on selection dag, and worst of all I can't use
lower since I write llvm ir into highlevel code (like CBackend)
and therefore have to implement my own lower. Or do you
a better idea for this?
-Jochen
2013 Dec 03
0
[LLVMdev] Newbie question: LLVM IR, printf, and varargs
...gt; i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([5 x i8]* @.str1,
> i32 0, i32 0)) nounwind
> ret i32 0
> }
>
> declare i32 @printf(i8* nocapture readonly, ...) nounwind
>
> A good thing about this question is that the answer will find its way into
> the Mapping Highlevel doc, which is why I am asking it in the first place.
>
> This is on Windows using a 32-bit version of LLVM llc v3.4 (built about a
> week ago).
>
> I searched the LR, the FAQ, and Google but found nothing of relevance.
>
>
You're missing the cast, IMHO. The cast appeases th...
2010 Sep 04
1
[LLVMdev] Thoughts about the llvm architecture -
...lower
> combine
> legalize
> combine
> ...
>
> I wonder if there is duplicate code in instCombine (on llvm ir, e.g.
> llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp)
> and combine on selection dag, and worst of all I can't use
> lower since I write llvm ir into highlevel code (like CBackend)
> and therefore have to implement my own lower. Or do you
> a better idea for this?
>
> -Jochen
The same passes would be beneficial for my PTX backend
implementation(also like Cbackend). Are there reasons for not
implementing them on the llvm ir? Is the current im...
2011 Dec 29
0
[LLVMdev] InstCombine "pessimizes" trunc i8 to i1?
...e optimizer.
> >
> > Why do you consider this to be a pessimization? Does one produce
> inferior machine code?
>
> I consider it a pessimization as it is one additional instruction and
> I'm mainly interested in target
> independent optimizations because I regenerate highlevel code from it
> ("Exporting 3D scenes from Maya to WebGL using clang and llvm").
> For example from the given code before the transformation I can easily
> regenerate
> myGlobal ? 1.0f : -1.0f
> while after the transformation I get
> (myGlobal & 1) != 0 ? 1.0f : -1.0f...
2006 Jun 30
2
Advanced routing routing table limits and rule design
...e than 255. I realize this involves
increasing the storage of some messages to and from the kernel in
addition to kernel changes (from browsing the code), and was hopeful
that someone might know what the correct solution would be or could
point me in the right direction (like existing patches or a highlevel of
what I need to change in the code).
Additionally, I was curious how the ip *rule* system works in regards to
matching -- is it a linear search or optimized in some way. Basically
what I''m asking is if adding rules to a machine adds time to the whole
system passing over various rules t...
2006 Mar 23
4
ANN: capistrano-runit-tasks 0.2.0
I''d like to announce the second release of capistrano-runit-tasks,
available from http://rubyforge.org/projects/cappy-runit/
It now supports:
* File based templates
* sv as the service control command in addition to runsvctrl
* A much simpler interface for creating additional services.
More work still needs to be done though!
== TODO
* Allow add_service to create more than one
2013 Dec 03
0
[LLVMdev] Newbie question: LLVM IR, printf, and varargs
...i8]* @.str1,
>>> i32 0, i32 0)) nounwind
>>> ret i32 0
>>> }
>>>
>>> declare i32 @printf(i8* nocapture readonly, ...) nounwind
>>>
>>> A good thing about this question is that the answer will find its way
>>> into the Mapping Highlevel doc, which is why I am asking it in the first
>>> place.
>>>
>>> This is on Windows using a 32-bit version of LLVM llc v3.4 (built about
>>> a week ago).
>>>
>>> I searched the LR, the FAQ, and Google but found nothing of relevance.
>>>...
2010 Sep 03
1
[LLVMdev] Thoughts about the llvm architecture -
On 2010-09-03 13:19, Jochen Wilhelmy wrote:
>
>>> Hi!
>>>
>>> The following thoughts about the llvm architecture I'd like to share
>>> with you
>>> (from the perspective of a user):
>>>
>>> - If a backend has no vector support, then I wonder why there is no
>>> de-vectorization
>>> pass that operates on
2013 Dec 03
2
[LLVMdev] Newbie question: LLVM IR, printf, and varargs
...2 0, i32 0)) nounwind
>>>> ret i32 0
>>>> }
>>>>
>>>> declare i32 @printf(i8* nocapture readonly, ...) nounwind
>>>>
>>>> A good thing about this question is that the answer will find its way
>>>> into the Mapping Highlevel doc, which is why I am asking it in the first
>>>> place.
>>>>
>>>> This is on Windows using a 32-bit version of LLVM llc v3.4 (built about
>>>> a week ago).
>>>>
>>>> I searched the LR, the FAQ, and Google but found nothing of...
2013 Dec 04
0
[LLVMdev] Newbie question: LLVM IR, printf, and varargs
...t;>>> ret i32 0
>>>>> }
>>>>>
>>>>> declare i32 @printf(i8* nocapture readonly, ...) nounwind
>>>>>
>>>>> A good thing about this question is that the answer will find its way
>>>>> into the Mapping Highlevel doc, which is why I am asking it in the first
>>>>> place.
>>>>>
>>>>> This is on Windows using a 32-bit version of LLVM llc v3.4 (built
>>>>> about a week ago).
>>>>>
>>>>> I searched the LR, the FAQ, and Goo...
2016 Dec 09
2
[Qemu-devel] [PATCH kernel v5 0/5] Extend virtio-balloon for fast (de)inflating & fast live migration
> On 12/08/2016 08:45 PM, Li, Liang Z wrote:
> > What's the conclusion of your discussion? It seems you want some
> > statistic before deciding whether to ripping the bitmap from the ABI,
> > am I right?
>
> I think Andrea and David feel pretty strongly that we should remove the
> bitmap, unless we have some data to support keeping it. I don't feel as
>
2016 Dec 09
2
[Qemu-devel] [PATCH kernel v5 0/5] Extend virtio-balloon for fast (de)inflating & fast live migration
> On 12/08/2016 08:45 PM, Li, Liang Z wrote:
> > What's the conclusion of your discussion? It seems you want some
> > statistic before deciding whether to ripping the bitmap from the ABI,
> > am I right?
>
> I think Andrea and David feel pretty strongly that we should remove the
> bitmap, unless we have some data to support keeping it. I don't feel as
>
2005 May 13
1
FreeBSD Security Advisory FreeBSD-SA-05:09.htt [REVISED]
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
=============================================================================
FreeBSD-SA-05:09.htt Security Advisory
The FreeBSD Project
Topic: information disclosure when using HTT
Category: core
Module: sys
Announced: