search for: highlatency

I'm unclear how does DFAPacketizer and the scheduler know a given instruction is a load. Here is what I'm talking about Let's assume my VLIW target is described as follows: def MyTargetItineraries : ProcessorItineraries<[Slot0, Slot1], [], [ .............................. InstrItinData<RI, [InstrStage<1, [Slot0, Slot1]>]>,

...ncy(const MCSchedModel *SchedModel, const MachineInstr *DefMI) const; This is currently non-virtual because it is designed to directly query the fields in the SchedMachineModel tablegen class using another hook to select high latency ops: virtual bool isHighLatencyDef(int opc) const; Instructions that are not high latency default to one cycle. Example: def GenericModel : SchedMachineModel { let LoadLatency = 4; let HighLatency = 10; } If it really helps, you could redeclare defaultDefLatency as a virtual hook and override it. (2) The "old"...

...ef based on it's opcode. > unsigned TargetInstrInfo::defaultDefLatency( > const MCSchedModel &SchedModel, const MachineInstr *DefMI) const { > if (DefMI->isTransient()) > return 0; > if (DefMI->mayLoad()) > return SchedModel.LoadLatency; > if (isHighLatencyDef(DefMI->getOpcode())) > return SchedModel.HighLatency; > return 1; > } > > > -Krzysztof > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The Linux Foundation > _______________________________________________ > LLV...

I just updated to RELENG_7 from 6.2 and I'm running into some really annoying issues with jerky mouse movement and skipping sound. This seems to be similar to: Re: SCHED_4BSD in RELENG_7 disturbs workflow This happens both with 4BSD and ULE. I seems to happen when I'm compiling ports and a new cc/bzip2/sh process fires off (I'm just watching top), I'll get the skip/freezeup.