Displaying 9 results from an estimated 9 matches for "hi_comp".
2012 Sep 05
5
[LLVMdev] 64 bit special purpose registers
...sters and
> only using that register class as an operand in the instructions where it
> is legal.
> You then set as sub registers what you want to represent as the hi and lo
> registers for those 64bit registers.
>
> So something like this:
> def lo_comp : SubRegIndex;
> def hi_comp : SubRegIndex;
> def R1 : Register<1>;
> def R2 : Register<2>;
> def R3 : Register<1>;
> def R4 : Register<2>;
> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
>
> This says that D1 is a register with two components, lo and hi. When...
2012 Aug 07
0
[LLVMdev] 64 bit special purpose registers
...laring a register class with these registers and only using that register class as an operand in the instructions where it is legal.
You then set as sub registers what you want to represent as the hi and lo registers for those 64bit registers.
So something like this:
def lo_comp : SubRegIndex;
def hi_comp : SubRegIndex;
def R1 : Register<1>;
def R2 : Register<2>;
def R3 : Register<1>;
def R4 : Register<2>;
def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
This says that D1 is a register with two components, lo and hi. When you allocate D1, you also use R1/...
2012 Aug 06
2
[LLVMdev] 64 bit special purpose registers
On Mips 32 there is traditionally a 64 bit HI/LO register for the result
of multiplying two 64 bit numbers.
There are corresponding instructions to load the LO and HI parts into
individual 32 registers.
On Mips with the DSP ASE (an application specific extension), there are
actual 4 such pairs of
registers.
Is there a way to have special purpose 64 bit registers without actually
having to
2012 Sep 06
0
[LLVMdev] 64 bit special purpose registers
...g that register class as an operand in the
> instructions where it is legal.
> You then set as sub registers what you want to represent as the hi
> and lo registers for those 64bit registers.
>
> So something like this:
> def lo_comp : SubRegIndex;
> def hi_comp : SubRegIndex;
> def R1 : Register<1>;
> def R2 : Register<2>;
> def R3 : Register<1>;
> def R4 : Register<2>;
> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
>
> This says that D1 is a register with two com...
2012 Sep 05
0
[LLVMdev] 64 bit special purpose registers
...laring a register class with these registers and only using that register class as an operand in the instructions where it is legal.
You then set as sub registers what you want to represent as the hi and lo registers for those 64bit registers.
So something like this:
def lo_comp : SubRegIndex;
def hi_comp : SubRegIndex;
def R1 : Register<1>;
def R2 : Register<2>;
def R3 : Register<1>;
def R4 : Register<2>;
def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
This says that D1 is a register with two components, lo and hi. When you allocate D1, you also use R1/...
2012 Sep 07
1
[LLVMdev] 64 bit special purpose registers
...at register class as an operand in the instructions where it
>> is legal.
>> You then set as sub registers what you want to represent as the hi and lo
>> registers for those 64bit registers.
>>
>> So something like this:
>> def lo_comp : SubRegIndex;
>> def hi_comp : SubRegIndex;
>> def R1 : Register<1>;
>> def R2 : Register<2>;
>> def R3 : Register<1>;
>> def R4 : Register<2>;
>> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
>>
>> This says that D1 is a register with two...
2012 Sep 06
3
[LLVMdev] 64 bit special purpose registers
...operand in the
>> instructions where it is legal.
>> You then set as sub registers what you want to represent as the
>> hi and lo registers for those 64bit registers.
>>
>> So something like this:
>> def lo_comp : SubRegIndex;
>> def hi_comp : SubRegIndex;
>> def R1 : Register<1>;
>> def R2 : Register<2>;
>> def R3 : Register<1>;
>> def R4 : Register<2>;
>> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
>>
>> This says that D...
2012 Sep 06
0
[LLVMdev] 64 bit special purpose registers
...at register class as an operand in the instructions where it is
>> legal.
>> You then set as sub registers what you want to represent as the hi and lo
>> registers for those 64bit registers.
>>
>> So something like this:
>> def lo_comp : SubRegIndex;
>> def hi_comp : SubRegIndex;
>> def R1 : Register<1>;
>> def R2 : Register<2>;
>> def R3 : Register<1>;
>> def R4 : Register<2>;
>> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
>>
>> This says that D1 is a register with two...
2012 Sep 07
1
[LLVMdev] 64 bit special purpose registers
...ctions where
> it is
> >> legal.
> >> You then set as sub registers what you want to represent as the hi and
> lo
> >> registers for those 64bit registers.
> >>
> >> So something like this:
> >> def lo_comp : SubRegIndex;
> >> def hi_comp : SubRegIndex;
> >> def R1 : Register<1>;
> >> def R2 : Register<2>;
> >> def R3 : Register<1>;
> >> def R4 : Register<2>;
> >> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
> >>
> >> This...