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...int-after=codegenprepare -mcpu=cortex-a53 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA <%t %s And the worst thing I witnessed was with the Hexagon back-end were my changes in DAGCombiner trigger an Unreachable: home/dev/llvm/build/./bin/llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr < /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll | /home/dev/llvm/build/./bin/FileCheck /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll -- Exit Code: 2 Command Output (stderr): -- ReplaceNodeResults not implemented for this target! UNREACHABLE...

...-mcpu=cortex-a53 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA > <%t %s > > And the worst thing I witnessed was with the Hexagon back-end were my > changes in DAGCombiner trigger an Unreachable: > > home/dev/llvm/build/./bin/llc -march=hexagon -mcpu=hexagonv5 > -disable-hsdr < > /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll | > /home/dev/llvm/build/./bin/FileCheck > /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll > -- > Exit Code: 2 > > Command Output (stderr): > -- > ReplaceNodeResults...

...lt; %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA > <%t %s > > And the worst thing I witnessed was with the Hexagon back-end were my > changes in DAGCombiner trigger an Unreachable: > > home/dev/llvm/build/./bin/llc -march=hexagon -mcpu=hexagonv5 > -disable-hsdr < > /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll | > /home/dev/llvm/build/./bin/FileCheck > /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll > -- > Exit Code: 2 > > Command Output (stderr): &gt...

...mp; FileCheck > --check-prefix=CHECK-UseAA > > <%t %s > > > > And the worst thing I witnessed was with the Hexagon back-end were my > > changes in DAGCombiner trigger an Unreachable: > > > > home/dev/llvm/build/./bin/llc -march=hexagon -mcpu=hexagonv5 > > -disable-hsdr < > > /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll | > > /home/dev/llvm/build/./bin/FileCheck > > /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll > > -- > > Exit Code: 2 > > &gt...

...-UseAA > >     <%t %s > > > >     And the worst thing I witnessed was with the Hexagon back-end > were my > >     changes in DAGCombiner trigger an Unreachable: > > > >     home/dev/llvm/build/./bin/llc -march=hexagon -mcpu=hexagonv5 > >     -disable-hsdr < > >     /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll | > >     /home/dev/llvm/build/./bin/FileCheck > >     /home/dev/llvm/llvm/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll > >     -- > > ...

For the tests that are changing, you should see if those changes are improvements, regressions, or neutral. This is unfortunately not always obvious for x86 asm, so feel free to just post those diffs in an updated version of the patch at D37896. If the test files have auto-generated assertions (look for this string on the first line of the test file: "NOTE: Assertions have been autogenerated

...take some time to review this patch. This patch does not yield any warnings on Hexagon, Arm and X86 build on Linux. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: HexagonV5-FP-Support-cfe.patch URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120419/f1b8c596/attachment.ksh>

...take some time to review this patch. This patch does not yield any warnings on Hexagon, Arm and X86 build on Linux. Sirish -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: HexagonV5-FP-Support-llvm.patch URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120419/b015a7b6/attachment.ksh>

Hi all, I want to generate assembly code using Swing Modulo Scheduling in LLVM for many ALU (May could be Adders, multilayer ......), I need some help how I can do that, which commend I run? Also if possible more information about the scheduling and the register location ......, and which pass responsible about that, and which LLVM version support Swing Modulo Scheduling. Thank you. Regards