Displaying 2 results from an estimated 2 matches for "hexagonmcinstlow".
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hexagonmcinstlower
2016 Feb 16
2
a bundle with one instruction
>
> No problem. At some point the machine instructions represented by a class
> "MachineInstr" are transformed into a representation using class "MCInst".
> This is the MC level I'm talking about. It's the representation that the
> llvm-mc uses.
>
>
Do you mind pointing out where in the code this is happening?
--
Rail Shafigulin
Software
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...;> + bool isEndPacket() const { return (endPacket); };
>> +
>> + void setStartPacket(bool yes) { startPacket = yes; };
>> + void setEndPacket(bool yes) { endPacket = yes; };
>> + };
>> +}
>> +
>> +#endif
>> diff --git a/lib/Target/Hexagon/HexagonMCInstLower.cpp b/lib/Target/Hexagon/HexagonMCInstLower.cpp
>> index fbb331b..70bddcc 100644
>> --- a/lib/Target/Hexagon/HexagonMCInstLower.cpp
>> +++ b/lib/Target/Hexagon/HexagonMCInstLower.cpp
>> @@ -49,7 +49,7 @@ void llvm::HexagonLowerToMC(const MachineInstr* MI, MCInst& MCI,...