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...ab80, OldIdx=...) at lib/CodeGen/LiveIntervalAnalysis.cpp:938 #8 in llvm::LiveIntervals::handleMove (this=0x448b6f0, MI=0x462ab80) at lib/CodeGen/LiveIntervalAnalysis.cpp:1388 #9 in llvm::VLIWMachineScheduler::moveInstruction (this=0x46b0f50, MI=0x462ab80, InsertPos=...) at lib/Target/Hexagon/HexagonMachineScheduler.cpp:120 #10 in llvm::VLIWMachineScheduler::schedule (this=0x46b0f50) at lib/Target/Hexagon/HexagonMachineScheduler.cpp:378 #11 in (anonymous namespace)::MachineScheduler::runOnMachineFunction (this=0x448c730, mf=...) at lib/CodeGen/MachineScheduler.cpp:263 #12 in llvm::MachineFunctionPass::runO...

On Aug 13, 2012, at 8:34 AM, Sergei Larin <slarin at codeaurora.org> wrote: > Andy, > > Yes, this is what Arnold has suggested also, and from this point it looks > like it should work, but it will require parsing the bundle every time we > care to know whether this is a real use or a conditional def. This might > become awkward... but I guess I should provide a better

...Gen/LiveIntervalAnalysis.cpp:938 > #8 in llvm::LiveIntervals::handleMove (this=0x448b6f0, MI=0x462ab80) > at > lib/CodeGen/LiveIntervalAnalysis.cpp:1388 > #9 in llvm::VLIWMachineScheduler::moveInstruction (this=0x46b0f50, > MI=0x462ab80, InsertPos=...) at > lib/Target/Hexagon/HexagonMachineScheduler.cpp:120 > #10 in llvm::VLIWMachineScheduler::schedule (this=0x46b0f50) at > lib/Target/Hexagon/HexagonMachineScheduler.cpp:378 > #11 in (anonymous namespace)::MachineScheduler::runOnMachineFunction > (this=0x448c730, mf=...) at lib/CodeGen/MachineScheduler.cpp:263 > #12 in llvm::...

.... Simplifying the problem, only loop free code will be processed. Further, preparations and studies of llvm framework have shown, that, in my humble opinion, the machineScheduler::runOnMachineFunction() would be the best place to start with. Later the code will be put into a separate class like the HexagonMachineScheduler and the MachineScheduler will be reverted back to it's original state. This is an outline of my concept on how to implement this basic trace scheduling approach. Progressing in this plan, I encountered different problems. The first one is about the compiler infrastructure with its passes. I...

Hi, Thanks for your explanations! How is the big picture for supporting in-order VLIW architectures and the like though? I am asking because I am currently implementing instruction scheduling in our own backend for our custom Patmos processor, for which I need to support both branch delay slots and bundles, some restrictions regarding bundles. For the moment, I am quite happy with a simple