search for: hexagonisd

...an parse Relations defs and emit the information into tabular form. I expect to index the resulting table using the instruction opcode and find opcode of the new instruction of the desired format. Any suggestions will be much appreciated. Relationship table layout: HexagonInstrRelations[] = { . {HexagonISD::ADDrr, HexagonISD::ADDrr, HexagonISD:: ADDrr_p, HexagonISD::ADDrr_np}, {HexagonISD::ADDrr_p, HexagonISD::ADDrr, -1, -1}, {HexagonISD::ADDrr_np, HexagonISD::ADDrr, -1, -1}, . }; Each column represents a specific relationship, -1 means 'invalid/nonexistent relation'. Thanks, Jyotsna ---...

...ts. Just an idea, you may know that it's possible to custom expand operations with illegal types and it might be useful in this case (considering i1 as illegal). The TypeLegalizer will callback to your lowering function at the very beginning of the Combining/Legalization phases. If you add HexagonISD nodes in the process while promoting operands/result, you will be able to precisely match them later with its associated regclass (PReg?). Unfortunately, it will not resolve your problem with non-allowed ops for i8 types and I think I'm missing something regarding this matter. Why don't...

On Thu, May 24, 2012 at 5:06 PM, Hal Finkel <hfinkel at anl.gov> wrote: > Sebastian, > > First, it might be useful to look at what is done in the PowerPC > backend. PPC also has condition registers that are larger than the > 1-bit conditional results, and it defines 1-bit subregisters in > addition to the larger condition registers. The spill-restore code ends > up being

Sebastian, First, it might be useful to look at what is done in the PowerPC backend. PPC also has condition registers that are larger than the 1-bit conditional results, and it defines 1-bit subregisters in addition to the larger condition registers. The spill-restore code ends up being more complicated, but that, perhaps, is a separate issue. [To be clear, I am not advocating for (or against)

...1 in { >> - def ALLOCFRAME : STInst<(outs), >> + def ALLOCFRAME : STInst2<(outs), >> (ins i32imm:$amt), >> "allocframe(#$amt)", >> []>; >> @@ -2232,7 +2232,7 @@ def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDHexagonBARRIER, >> [SDNPHasChain]>; >> >> let hasSideEffects = 1 in >> -def BARRIER : STInst<(outs), (ins), >> +def BARRIER : STInst2<(outs), (ins), >> "barrier", >>...