Displaying 6 results from an estimated 6 matches for "hexagondagtodagisel".
2017 Sep 22
0
[Hexagon] Type Legalization
...r the given vector type.
if ( TLI.isOperationLegal(ISD::SUB, VT)
&& TLI.isOperationLegal(ISD::ADD, VT)
&& TLI.isOperationLegal(ISD::SHL, VT)
&& TLI.isOperationLegal(ISD::SRA, VT)) {
The Hexagon backend says happily: yes! Go ahead!
When it comes to HexagonDAGToDAGISel and the type should be legalized no
custom lowering is found and TargetLowering::ReplaceNodeResults is
called which falls back to the default implementation and the
unreachable is trigged.
Is this really working as intended or am I missing something here?
Cheers,
Michael
On 20.09.2017 16:10,...
2017 Sep 22
2
[Hexagon] Type Legalization
...if ( TLI.isOperationLegal(ISD::SUB, VT)
> && TLI.isOperationLegal(ISD::ADD, VT)
> && TLI.isOperationLegal(ISD::SHL, VT)
> && TLI.isOperationLegal(ISD::SRA, VT)) {
>
> The Hexagon backend says happily: yes! Go ahead!
> When it comes to HexagonDAGToDAGISel and the type should be legalized no
> custom lowering is found and TargetLowering::ReplaceNodeResults is
> called which falls back to the default implementation and the
> unreachable is trigged.
>
> Is this really working as intended or am I missing something here?
>
> Cheers,...
2017 Sep 20
3
Updating LLVM Tests for Patch
...../lib/libLLVMSelectionDAG.so.6+0x211fd8)
> #14 0x00007f1b2d7930e2
> llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&)
> [clone .part.873]
> (/home/dev/llvm/build/bin/../lib/libLLVMSelectionDAG.so.6+0x2140e2)
> #15 0x00007f1b35931d6a (anonymous
> namespace)::HexagonDAGToDAGISel::runOnMachineFunction(llvm::
> MachineFunction&)
> (/home/dev/llvm/build/bin/../lib/libLLVMHexagonCodeGen.so.6+0x116d6a)
> #16 0x00007f1b2ef22585
> llvm::MachineFunctionPass::runOnFunction(llvm::Function&)
> (/home/dev/llvm/build/bin/../lib/libLLVMCodeGen.so.6+0x21f585)
>...
2017 Sep 22
0
[Hexagon] Type Legalization
...gal(ISD::SUB, VT)
> && TLI.isOperationLegal(ISD::ADD, VT)
> && TLI.isOperationLegal(ISD::SHL, VT)
> && TLI.isOperationLegal(ISD::SRA, VT)) {
>
> The Hexagon backend says happily: yes! Go ahead!
> When it comes to HexagonDAGToDAGISel and the type should be legalized no
> custom lowering is found and TargetLowering::ReplaceNodeResults is
> called which falls back to the default implementation and the
> unreachable is trigged.
>
> Is this really working as intended or am I missing something here?
&...
2017 Sep 20
0
Updating LLVM Tests for Patch
...(/home/dev/llvm/build/bin/../lib/libLLVMSelectionDAG.so.6+0x211fd8)
#14 0x00007f1b2d7930e2
llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&)
[clone .part.873]
(/home/dev/llvm/build/bin/../lib/libLLVMSelectionDAG.so.6+0x2140e2)
#15 0x00007f1b35931d6a (anonymous
namespace)::HexagonDAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&)
(/home/dev/llvm/build/bin/../lib/libLLVMHexagonCodeGen.so.6+0x116d6a)
#16 0x00007f1b2ef22585
llvm::MachineFunctionPass::runOnFunction(llvm::Function&)
(/home/dev/llvm/build/bin/../lib/libLLVMCodeGen.so.6+0x21f585)
#17 0x00007f1b2e922dd3
llvm...
2017 Sep 19
5
How to add optimizations to InstCombine correctly?
For the tests that are changing, you should see if those changes are
improvements, regressions, or neutral. This is unfortunately not always
obvious for x86 asm, so feel free to just post those diffs in an updated
version of the patch at D37896.
If the test files have auto-generated assertions (look for this string on
the first line of the test file: "NOTE: Assertions have been autogenerated