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...[experimental] mipsel - Mipsel msp430 - MSP430 [experimental] nvptx - NVIDIA PTX 32-bit nvptx64 - NVIDIA PTX 64-bit ppc32 - PowerPC 32 ppc64 - PowerPC 64 ppc64le - PowerPC 64 LE r600 - AMD GPUs HD2XXX-HD6XXX sparc - Sparc sparcel - Sparc LE sparcv9 - Sparc V9 systemz - SystemZ thumb - Thumb thumbeb - Thumb (big endian) x86 - 32-bit X86: Pentium-Pro and above x86-64 - 64-bit X86: EM64T and AMD64 xcor...

...ntal] mips64el - Mips64el [experimental] mipsel - Mipsel msp430 - MSP430 [experimental] nvptx - NVIDIA PTX 32-bit nvptx64 - NVIDIA PTX 64-bit ppc32 - PowerPC 32 ppc64 - PowerPC 64 ppc64le - PowerPC 64 LE r600 - AMD GPUs HD2XXX-HD6XXX sparc - Sparc sparcv9 - Sparc V9 systemz - SystemZ thumb - Thumb thumbeb - Thumb (big endian) x86 - 32-bit X86: Pentium-Pro and above x86-64 - 64-bit X86: EM64T and AMD64 xcore - XCore -------------- next part -------------- An HTML...

...430 - MSP430 [experimental] >> nvptx - NVIDIA PTX 32-bit >> nvptx64 - NVIDIA PTX 64-bit >> ppc32 - PowerPC 32 >> ppc64 - PowerPC 64 >> ppc64le - PowerPC 64 LE >> r600 - AMD GPUs HD2XXX-HD6XXX >> sparc - Sparc >> sparcel - Sparc LE >> sparcv9 - Sparc V9 >> systemz - SystemZ >> thumb - Thumb >> thumbeb - Thumb (big endian) >> x86 - 32-bit X86: Pentium-Pro and abov...

...mental] > nvptx - NVIDIA PTX 32-bit > nvptx64 - NVIDIA PTX 64-bit > ppc32 - PowerPC 32 > ppc64 - PowerPC 64 > ppc64le - PowerPC 64 LE > r600 - AMD GPUs HD2XXX-HD6XXX > sparc - Sparc > sparcel - Sparc LE > sparcv9 - Sparc V9 > systemz - SystemZ > thumb - Thumb > thumbeb - Thumb (big endian) > x86 - 32-b...

...med by AMD's Open > Source 3D/Compute drivers which are part of the Mesa3D[1] project. The > backend is integrated into the driver, so you don't need to compile > shaders offline. Currently we are using the backend for graphics and > compute shaders in our r600g driver (HD2xxx-HD6xxx GPUs) and for graphics > in our radeonsi (HD7xxx GPUs). In the future we will use it for compute > shaders on radensi too. > > In order to use the backend for graphics on r600g, you need to build > Mesa with the --enable-r600-llvm-compiler option. For compute the > installation...

...is meant to be consumed by AMD's Open Source 3D/Compute drivers which are part of the Mesa3D[1] project. The backend is integrated into the driver, so you don't need to compile shaders offline. Currently we are using the backend for graphics and compute shaders in our r600g driver (HD2xxx-HD6xxx GPUs) and for graphics in our radeonsi (HD7xxx GPUs). In the future we will use it for compute shaders on radensi too. In order to use the backend for graphics on r600g, you need to build Mesa with the --enable-r600-llvm-compiler option. For compute the installation instructions are here: http:/...

...rce 3D/Compute drivers which are part of the Mesa3D[1] > > > project. The backend is integrated into the driver, so you don't > > > need to compile shaders offline. Currently we are using the backend > > > for graphics and compute shaders in our r600g driver (HD2xxx-HD6xxx > > > GPUs) and for graphics in our radeonsi (HD7xxx GPUs). In the future > > > we will use it for compute shaders on radensi too. > > > > > > In order to use the backend for graphics on r600g, you need to build > > > Mesa with the --enable-r600-llvm-co...

...n > > Source 3D/Compute drivers which are part of the Mesa3D[1] project. The > > backend is integrated into the driver, so you don't need to compile > > shaders offline. Currently we are using the backend for graphics and > > compute shaders in our r600g driver (HD2xxx-HD6xxx GPUs) and for graphics > > in our radeonsi (HD7xxx GPUs). In the future we will use it for compute > > shaders on radensi too. > > > > In order to use the backend for graphics on r600g, you need to build > > Mesa with the --enable-r600-llvm-compiler option. For compu...

...drivers which are part of the Mesa3D[1] > > > > project. The backend is integrated into the driver, so you don't > > > > need to compile shaders offline. Currently we are using the backend > > > > for graphics and compute shaders in our r600g driver (HD2xxx-HD6xxx > > > > GPUs) and for graphics in our radeonsi (HD7xxx GPUs). In the future > > > > we will use it for compute shaders on radensi too. > > > > > > > > In order to use the backend for graphics on r600g, you need to build > > > > Mesa with...

Hi! I'm trying to figure out how to access the workgroup id from within the LLVM IR language when lowering with the AMDGPU backend. Looking at the 'llvm/include/llvm/IR/IntrinsicsAMDGPU.td' file there are intrinsics defined to access the workitem index (thread index), but this file lives in 'llvm/include':

...mental] >>> nvptx - NVIDIA PTX 32-bit >>> nvptx64 - NVIDIA PTX 64-bit >>> ppc32 - PowerPC 32 >>> ppc64 - PowerPC 64 >>> ppc64le - PowerPC 64 LE >>> r600 - AMD GPUs HD2XXX-HD6XXX >>> sparc - Sparc >>> sparcel - Sparc LE >>> sparcv9 - Sparc V9 >>> systemz - SystemZ >>> thumb - Thumb >>> thumbeb - Thumb (big endian) >>> x86 - 32-b...

Hi Tom, As far as I can tell EmitLiveInCopies is just there to handle physreg arguments and return values. Is there any reason for these to change late in your backend? - Lang. On Tue, Feb 14, 2012 at 7:22 AM, Tom Stellard <thomas.stellard at amd.com>wrote: > On Mon, Feb 13, 2012 at 10:17:11PM -0800, Lang Hames wrote: > > Hi Tom, > > > > I'm pretty sure this

Hi Tom, I have a higher-level question regarding this back-end. If I have an LLVM IR module and run it through this back-end, it seems like the only output option is a binary format. Is this a device binary, or another intermediate format? If the input LLVM IR module was a compute kernel, how would I go about executing it on an AMD GPU? Can I use the APP SDK to load the binary, perhaps

...ed through the LLVM test > suite. My understanding of Tom's R600 back-end is that it only works in > conjunction with Mesa/Gallium, so verification on real hardware cannot > easily be done (please correct me if I am wrong here). > Assuming you have supported hardware (AMD HD2XXX - HD6XXX GPUs), all you need to do to verify the R600 compiler is download the latest development version of Mesa[1], configure with --enable-r600-llvm-compiler (if you want to use it for 3D apps) and/or --enable-opencl (if you want to use it for OpenCL programs, this requires a patched clang/llvm at the mo...

On Mon, Feb 13, 2012 at 10:17:11PM -0800, Lang Hames wrote: > Hi Tom, > > I'm pretty sure this function should only ever be called once, by > SelectionDAG. Do you know where the second call is coming from in your code? > > Cheers, > Lang. Hi Lang, I was calling EmitLiveInCopies() from one of my backend specific passes. If the function can only be called once, then

On Sat, Jul 21, 2012 at 8:08 PM, Chris Lattner <clattner at apple.com> wrote: > On Jul 20, 2012, at 8:51 AM, Tom Stellard wrote: > > The goals of the staging area will be: > > 1. Facilitate communication between the LLVM project and backend > > developers > > 2. Ensure that new backends meet LLVM standards > > 3. Give the backend more exposure to

...ice()->getStackAlignment(), 0), > + IntrinsicInfo(this), > + InstrItins(&Subtarget.getInstrItineraryData()), > + mDump(false) > + > +{ > + // TLInfo uses InstrInfo so it must be initialized after. > + if (Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) { > + InstrInfo = new R600InstrInfo(*this); > + TLInfo = new R600TargetLowering(*this); > + } else { > + InstrInfo = new SIInstrInfo(*this); > + TLInfo = new SITargetLowering(*this); > + } > +} > + > +AMDGPUTargetMachine::~AMDGPUTargetMachine() > +{ >...

Hi, I'm working on a custom top-down post RA scheduler which builds bundles at the same time for our VLIW processor. I've borrowed most of the implementation from the resource priority queue implemented for the existent VLIW scheduler but applied to the context of MI scheduling. Basically, instructions that are likely to be bundled must be scheduled first (i.e. get higher priority).