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2010/1/25 任坤 <hbrenkun at yahoo.cn>: > Hi: > > I hope to cut all backedges of MachineFunction CFG, then topological sort MachineBasicBlocks. > > 1. MachineDominatorTree *domintree = new MachineDominatorTree(); > domintree->runOnMachineFunction(mf); > > 2. Then travel mf one by one. >...

...-type-dags" option. By the way, I use llvm 2.5 merged from llvm2.4. Best Regards, Ren Kun --- 09年3月31日，周二, Evan Cheng <echeng at apple.com> 写道： 发件人: Evan Cheng <echeng at apple.com> 主题: Re: [LLVMdev] Dear Evan Chang, Re: help: about how to use tblgen to constraint operand. 收件人: hbrenkun at yahoo.cn, "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> 日期: 2009,331,周二,1:04上午 This is probably instruction selection issue. I would look at the dag at various stafes of isel. Try -view-legalize-type-dags, -view-legalize-dags, etc. Evan On Mar 29, 2009, at 11:54 PM, 任...

Hi: I hope to cut all backedges of MachineFunction CFG, then topological sort MachineBasicBlocks. 1. MachineDominatorTree *domintree = new MachineDominatorTree(); domintree->runOnMachineFunction(mf); 2. Then travel mf one by one. When domintree->dominates(next,current) is true, there is a backedge from current node to next node. move this backedge form CFG. But I find A LOOP in

...inatorTree.jpg is a previous exmaple. best regards! renkun --- 10年3月9日，周二, Nick Lewycky <nicholas at mxc.ca> 写道： > 发件人: Nick Lewycky <nicholas at mxc.ca> > 主题: Re: [LLVMdev] Find all backedges of CFG by MachineDominatorTree. please look at my jpg. > 收件人: "任坤" <hbrenkun at yahoo.cn> > 抄送: "Benoit Boissinot" <bboissin+llvm at gmail.com>, "llvm" <llvmdev at cs.uiuc.edu> > 日期: 2010年3月9日,周二,下午2:02 > 任坤   wrote: > > Hi: > >     I want to do some optimization > on MachineLoop. > > So I want to get MachineL...

...nd give it a virtual register number ,  I want to debug it to find error reason. Best Regards,    Ren Kun --- 09年2月21日，周六, Evan Cheng <evan.cheng at apple.com> 写道： 发件人: Evan Cheng <evan.cheng at apple.com> 主题: Re: [LLVMdev] help: about how to use tblgen to constraint operand. 收件人: hbrenkun at yahoo.cn, "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> 日期: 2009,221,周六,2:51上午 On Feb 19, 2009, at 8:26 PM, 任坤 wrote: hi, Dear Evan Cheng: My cpu is i32 embeded CPU. I define pseudo register pair registers. In mytargetRegisterInfo.td: def T0: RegisterWithSubRegs<...

Hi, EveryOne: I am travelling CFG with MachineFunction. So I want to sure it. (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really? best regards. ___________________________________________________________ 好玩贺卡等你发，邮箱贺卡全新上线！ http://card.mail.cn.yahoo.com/ -------------- next part -------------- An HTML attachment was scrubbed...

...I think the best way is that TableGen has register pair TypeProfile feature. :( But I find i64 data will not be ex --- 09年2月20日，周五, Evan Cheng <echeng at apple.com> 写道： 发件人: Evan Cheng <echeng at apple.com> 主题: Re: [LLVMdev] help: about how to use tblgen to constraint operand. 收件人: hbrenkun at yahoo.cn, "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu> 日期: 2009,220,周五,1:11上午 Currently there is no constraint that tells the register allocator to allocate a consecutive register pair. What I would suggest you do is to declare pseudo register pair registers (and corr...

...s different ?? Thanks. Ren Kun --- 10年1月26日，周二, Benoit Boissinot <bboissin+llvm at gmail.com> 写道： > 发件人: Benoit Boissinot <bboissin+llvm at gmail.com> > 主题: Re: [LLVMdev] Find all backedges of CFG by MachineDominatorTree.  please look at my jpg. > 收件人: "任坤" <hbrenkun at yahoo.cn> > 抄送: "llvm" <llvmdev at cs.uiuc.edu> > 日期: 2010年1月26日,周二,下午10:13 > On Tue, Jan 26, 2010 at 10:04:16PM > +0800, 浠诲潳   wrote: > > Hi, Dear Boissinot: > > > > 1. When I have irreducible CFG, I travel its nodes by > DFS. > >    se...

...not a trivial task. Evan > > > > > > But I find i64 data will not be ex > --- 09年2月20日，周五, Evan Cheng <echeng at apple.com> 写道： > 发件人: Evan Cheng <echeng at apple.com> > 主题: Re: [LLVMdev] help: about how to use tblgen to constraint > operand. > 收件人: hbrenkun at yahoo.cn, "LLVM Developers Mailing List" <llvmdev at cs.ui > uc.edu> > 日期: 2009,220,周五,1:11上午 > > Currently there is no constraint that tells the register allocator > to allocate a consecutive register pair. What I would suggest you do > is to declare pseud...

Hi 任坤, > void vfu1(union MYunion u) { > u.ui = 99; > } here u is passed by copy, so vfu1 has no externally visible effect. I think you meant: union MYunion *u > define void @vfu1(%struct.MYunion* byval align 4 %u) nounwind { Here "byval" means that a pointer to a temporary copy of u is being passed, not u itself. Thus any writes to the %u parameter have no effect

On Dec 3, 2009, at 9:52 PM, 任坤 wrote: > Hi, EveryOne: > > I am travelling CFG with MachineFunction. So I want to sure it. > (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really? > Hi 任坤, I can't say for sure, though I don't think we make assurances that this is the case. If you want to traverse the CFG, there should

On Dec 3, 2009, at 9:52 PM, 任坤 wrote: > I am travelling CFG with MachineFunction. So I want to sure it. > (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really? If the CFG contains loops, how could this be possible? Anyway, no you can't use MBB numbers for that. Perhaps you need the MachineDominatorTree analysis? Regards, /jakob

...ical sort. Am I right??? --- 10年1月26日，周二, Benoit Boissinot <bboissin+llvm at gmail.com> 写道： > 发件人: Benoit Boissinot <bboissin+llvm at gmail.com> > 主题: Re: [LLVMdev] Find all backedges of CFG by MachineDominatorTree. please look at my jpg. > 收件人: "任坤" <hbrenkun at yahoo.cn> > 日期: 2010年1月26日,周二,下午3:12 > On Tue, Jan 26, 2010 at 01:31:53PM > +0800, 浠诲潳   wrote: > > Hi, Dear Boissinot: > > > > If a graph(CFG) is irreducible, how to find every loop > headers of CFG? > > > > If I have a simple algorithm to find the...

On Jan 14, 2010, at 6:39 PM, 任坤 wrote: > But I want do some optimization after register alloction by adjusting > register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. You can also look at RegisterScavenging.cpp and MachineVerifier.cpp. They are doing the same

I am porting llvm-gcc frontend. We have ported GCC4.2 for our target. So I move *.h *.md and *.c to llvm-gcc.  I do not implement any LLVM MACRO, and use default action of llvm-gcc.  I get a new llvm-gcc for our target. But I get a bug. /******************************/ //#include <stdio.h> union MYunion {   unsigned char uc ;   int ui; } myunion; void vfu1(union MYunion  u) {     u.ui =

Hi, I have ported LLC to a risc cpu. It can pass benchmark that I have at current. But I want do some optimization after register alloction by adjusting register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. R4 is marked <kill> at MBB0. If I scan R4's

hi,      I am porting llvm to our embedded cpu. By my abi, long long type is aligned by 8 bytes. But now llvm-gcc frontend follows x86 abi, generate word-alignment LLVM-IR for va_arg().    In some degree, llvm-gcc frontend depends on targets. The best solution is llvm-gcc can create va_arg node, I can lower it at the backend.    Who can give a temporary solution to make frontend can create 8

Hi: I want add new Instrinsic for my target. So I first do some test. I add them in IntrinsicsPowerPC.td //===--------------------===// let TargetPrefix = "ppc" in { def int_ppc_mytest : Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>; } //===--------------------===// I add them in PPCInstrInfo.td //===--------------------===// def MYTEST : XForm_24_sync<31, 599, (outs), (ins),

Hi: I hope to cut all backedges of MachineFunction CFG, then topological sort MachineBasicBlocks. 1. MachineDominatorTree *domintree = new MachineDominatorTree(); domintree->runOnMachineFunction(mf); 2. Then travel mf one by one. When domintree->dominates(next,current) is true, there is a backedge from current node to next node. move this backedge form CFG. But I find A LOOP in

I define a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr. But I need to use an even/odd register pair to save its 2 operands. I define in mytarget.td: myfmdrr: SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,     SDTCisSameAs<1, 2>]>; def my_fmdrr : ........... def myFMDRR : ....                       (outs FPR: $result), ins(GPR: