Displaying 6 results from an estimated 6 matches for "hazardrec".
2019 Oct 04
2
[MachineScheduler]: SchedBoundary trivially copiable, but "HazardRec" is raw pointer: a design issue?
Hi to everyone,
while working with the machine scheduler for a personal project, I came
up with the necessity of
inserting a backup boundary in the MachineSchedulerStrategy -- specifically,
the PostGenericScheduler -- to hold a copy the scheduler's state, in
order to implement a really
trivial (and really inefficient) backtracking mechanism.
This approach leads to a subtle "segmentation
2012 Aug 13
1
[LLVMdev] [RFC] Bundling support in the PostRA Scheduler
Hi all,
Thanks for your feed-backs :-)
@Andrew: In fact, I've reused most of the postRA list scheduler code and
the resource priority queue. Every time it needs to move forward, either
because of a res hazard (HazardRec) or an invalid combination of
instructions in the current packet (DFA), it closes the current bundle
and advances to the next cycle. The non-interlocked nature of our
processor forces the bundling logic to live with the scheduling logic.
We cannot build bundles without the scoreboard.
I also t...
2017 Feb 11
2
Specify special cases of delay slots in the back end
...t doesn't advance at the next available instruction
- it always gets the same store. This might be because I did not specify in a file like
[Target]Schedule.td the functional units, processor and instruction itineraries.
Regarding the Stalls argument to my method
[Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the argument Stalls
= 0. This is no surprise since in PostRASchedulerList.cpp we have only one call to it, in
method SchedulePostRATDList::ListScheduleTopDown():
ScheduleHazardRecognizer::HazardType HT =
HazardRec->getHazardType(CurSUnit, 0/...
2012 Aug 06
0
[LLVMdev] [RFC] Bundling support in the PostRA Scheduler
On Jul 31, 2012, at 8:37 AM, Ivan Llopard <ivanllopard at gmail.com> wrote:
> Hi,
>
> I'm working on a custom top-down post RA scheduler which builds bundles
> at the same time for our VLIW processor. I've borrowed most of the
> implementation from the resource priority queue implemented for the
> existent VLIW scheduler but applied to the context of MI
2017 Feb 10
2
Specify special cases of delay slots in the back end
Hello.
I am progressing a bit with difficulty with the post RA scheduler
(PostRASchedulerList.cpp with ScoreboardHazardRecognizer) - the problem I have is that it
doesn't advance at the next available instruction when the overridden
ScoreboardHazardRecognizer::getHazardType() method returns NoopHazard and it gets stuck at
the same instruction (store in my runs).
Just to make sure: I am trying to use the pos...
2012 Jul 31
6
[LLVMdev] [RFC] Bundling support in the PostRA Scheduler
Hi,
I'm working on a custom top-down post RA scheduler which builds bundles
at the same time for our VLIW processor. I've borrowed most of the
implementation from the resource priority queue implemented for the
existent VLIW scheduler but applied to the context of MI scheduling.
Basically, instructions that are likely to be bundled must be scheduled
first (i.e. get higher priority).