Displaying 2 results from an estimated 2 matches for "hasvex_4vop3prefix".
2012 Jul 10
0
[LLVMdev] question on table gen TIED_TO constraint
I don't think changing to VEX_4VOp3 to VEX_4V is the right fix. I think the
fix is to increment CurOp twice at the start for these instructions so that
only the input operands are used for encoding.
Also, I just submitted a patch to revert the operand order for these
instructions in the assembler/disassembler. Destination register should
appear on the right and the mask should appear on the
2012 Jul 10
2
[LLVMdev] question on table gen TIED_TO constraint
Yes, there is an easy way to fix this.
MRMSrcMem assumes register, memory, vvvv register if VEX_4VOp3 is true and assumes register, vvvv register, memory if VEX_4V is true.
I just need to change the flag from VEX_4VOp3 to VEX_4V. There are a few places where we assume only the 2nd operand can be tied-to:
Desc->getOperandConstraint(1, MCOI::TIED_TO) != -1 (hard-coded index 1)
I will fix those