Displaying 5 results from an estimated 5 matches for "hasv7ops".
2015 Sep 25
2
Error compiling libc++ for ARMv6
...newly added emitAtomicCmpXchgNoStoreLLBalance()
function is the culprit. Does this seem like a resaonable fix, or do I
need to do something different for v6 and earlier?
void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
IRBuilder<> &Builder) const {
if (Subtarget->hasV7Ops()) {
Module *M = Builder.GetInsertBlock()->getParent()->getParent();
Builder.CreateCall(llvm::Intrinsic::getDeclaration(M,
Intrinsic::arm_clrex));
}
}
-Rich
2015 Sep 26
2
Error compiling libc++ for ARMv6
...>> function is the culprit. Does this seem like a resaonable fix, or do I need
>> to do something different for v6 and earlier?
>>
>> void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
>> IRBuilder<> &Builder) const {
>> if (Subtarget->hasV7Ops()) {
>> Module *M = Builder.GetInsertBlock()->getParent()->getParent();
>> Builder.CreateCall(llvm::Intrinsic::getDeclaration(M,
>> Intrinsic::arm_clrex));
>> }
>> }
For v6, I guess we could do a fake strex to some dummy global?
Anyway, r248640, sorry...
2016 Sep 19
3
[arm, aarch64] Alignment checking in interleaved access pass
...ned, but I cannot get a clear picture on the impact on
performance (hence the side question below).
Also, some preliminary alignment checks I added break some ARM tests (and
not their AArch64 counterparts). The cause is getting "not fast" from
allowsMisalignedMemoryAccesses, from checking hasV7Ops.
I'd appreciate getting some guidance one how to best address and analyze
this.
Side question for Tim and other ARM folks, could I get a recommendation on
reading material for performance tuning for the different ARM archs?
Thank you,
Alina
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2015 Sep 15
3
The Trouble with Triples
On 15 September 2015 at 19:34, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote:
> We can go further with this analogy too. For example, let's say John Smith
> with the SSN Y also answers to the name Rameses. This is the problem that
> Renato is working on. Renato needs to be able to see the name Rameses and
> map this to the correct John Smith (or at least someone very
2016 Oct 10
2
[arm, aarch64] Alignment checking in interleaved access pass
...pick that up from the cost analysis pass (2-way vs 4-way).
>
>
> > Also, some preliminary alignment checks I added break some ARM tests (and
> > not their AArch64 counterparts). The cause is getting "not fast" from
> > allowsMisalignedMemoryAccesses, from checking hasV7Ops.
>
> What do you mean by "break"? Bad codegen? Slower code?
>
>
> > Side question for Tim and other ARM folks, could I get a recommendation
> on
> > reading material for performance tuning for the different ARM archs?
>
> ARM has a list of manuals on each...