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...tervals having correct weights? > > The linscan allocator inserts spill code with infinite weight, take a look > at how it works. So, as far as I understood live intervals with weight equal to HUGE_VAL are spilled and I don't need to allocate physical registers for them, right? Shoud hasStackSlot method of VirtRegMap return true for these intervals' reg members? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20060821/d306aec5/attachment.html>

...is not spilled again, otherwise you may enter on an infinite loop, always spilling the same spilled register. Fernando > > So, as far as I understood live intervals with weight equal to HUGE_VAL are > spilled and I don't need to allocate physical registers for them, right? > Shoud hasStackSlot method of VirtRegMap return true for these intervals' reg > members? >

So what addIntervalsToSpills returns are new intervals to allocate with infinite weights, right? And I need not to allocate the old interval. Should hasStackSlot return true on its register then? On 8/21/06, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > Well, someone correct me if am wrong, but, you still have to allocate > physical registers to them, because their values must be reloaded before > been used. Bu...

> So what addIntervalsToSpills returns are new intervals to allocate with > infinite weights, right? > And I need not to allocate the old interval. Should hasStackSlot return true > on its register then? > I am not very sure about addIntervalsToSpill, but, for all the registers created to replace a spilled registers, they must have a stack slot assigned to them. I am sending you my spilling method, so you can have an example: //===------------------------...

...< mi->getNumOperands(); u++) { const MachineOperand & mo = mi->getOperand(u); if(mo.isUse() && mo.isRegister() && mo.getReg()) { if(MRegisterInfo::isVirtualRegister(mo.getReg())) { unsigned v_reg = mo.getReg(); if(this->vrm->hasStackSlot(v_reg)) { int slot = this->vrm->getStackSlot(v_reg); // First, try to fold the memory reference into the // instruction. If we can do this, we don't need to // insert spill code. const TargetMachine & target_machine =...

...rtualRegister(LIReg) || LIReg == VReg) continue; // **** Check to see if the physreg we assigned conflicts with something // **** else. If so, that thing has to live in memory too. if (VRM->hasPhys(LIReg) && VRM->getPhys(LIReg) == PReg && !VRM->hasStackSlot(LIReg) && Added[I]->overlaps(L)) VRM->assignVirt2StackSlot(LIReg); } } The two points I want to talk about are noted by the **** comments. The first takes a newly-created live interval to represent the lifetime between a reload and use of the reload (or def and store)...

Hi! I'm developing a register allocator that works iteratively. It spills some virtual registers on each iteration until all the rest have physical ones assigned. How can I spill some live intervals at the end of each iteration with new live intervals having correct weights? Thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL:

On Sun, 6 Aug 2006, Anton Vayvod wrote: > I'm developing a register allocator that works iteratively. It spills some > virtual registers on each iteration until all the rest have physical ones > assigned. Take a look at the linear scan allocator. It is also iterative: it uses the spiller interface to insert spill code, which creates (unspillable) intervals for the spill code it

...erands(); u++) { > const MachineOperand & mo = mi->getOperand(u); > if(mo.isUse() && mo.isRegister() && mo.getReg()) { > if(MRegisterInfo::isVirtualRegister(mo.getReg())) { > unsigned v_reg = mo.getReg(); > if(this->vrm->hasStackSlot(v_reg)) { > int slot = this->vrm->getStackSlot(v_reg); > // First, try to fold the memory reference into the > // instruction. If we can do this, we don't need to > // insert spill code. > const TargetMachine & targ...

...; VReg) continue; > > // **** Check to see if the physreg we assigned conflicts > with something > // **** else. If so, that thing has to live in memory too. > if (VRM->hasPhys(LIReg) && VRM->getPhys(LIReg) == PReg && > !VRM->hasStackSlot(LIReg) && Added[I]->overlaps(L)) > VRM->assignVirt2StackSlot(LIReg); > } > } > > The two points I want to talk about are noted by the **** > comments. The first > takes a newly-created live interval to represent the lifetime > between a reloa...

On Aug 13, 2006, at 11:16 PM, Fernando Magno Quintao Pereira wrote: > > Dear LLVMers, > > I am trying to fold memory operands in the way that is done in > RegAllocLocal.cpp, or in LiveIntervalAnalysis.cpp, but I am getting > errors > that > I don't know how to fix. Could someone tell me which steps should I > take > in order > to correctly fold memory

...h has a stack slot already? On 8/21/06, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > > So what addIntervalsToSpills returns are new intervals to allocate with > > infinite weights, right? > > And I need not to allocate the old interval. Should hasStackSlot return > true > > on its register then? > > > > I am not very sure about addIntervalsToSpill, but, for all the registers > created to replace a spilled registers, they must have a stack slot > assigned to them. I am sending you my spilling method, so you can have an >...

Dear LLVMers, I am trying to fold memory operands in the way that is done in RegAllocLocal.cpp, or in LiveIntervalAnalysis.cpp, but I am getting errors that I don't know how to fix. Could someone tell me which steps should I take in order to correctly fold memory operands? The code that I am using is: const TargetMachine & target_machine = this->machine_function->getTarget();