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...y MCRegUnitIterator and MCRegUnitRootIterator. Regunit live intervals are more strictly defined than the old physreg intervals. The same way a virtreg interval can be computed from all machine operands mentioning the virtreg, regunit intervals can be computed from all physreg operands with TRI->hasRegUnit(MO.getReg(), RegUnit). However, while virtreg live intervals have a one-to-one mapping with machine operands, regunit intervals have a many-to-many mapping with the operands. A single physreg operand can affect multiple regunit intervals, and a regunit interval can be affected by different (overla...

...patch. Sergei - could you let me know if this fixes your issue? Thanks again for all of your work tracking this down. > It is best to avoid the MCRegUnitRootIterator+MCSuperRegIterator > combination because the set of super-registers can be quite large on ARM. > Done. I've used TRI.hasRegUnit as suggested. Thanks for the advice! Cheers, Lang. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120912/5c00ae0a/attachment.html>

Hi Jakob, I've got a good test case that I'm working on at the moment. I noticed something odd though: Is '0' a valid register unit? I'm seeing a LiveInterval with li->reg == 0 show up, which previously wasn't valid. We have a few checks around the place to disregard the '0' physreg - could these trigger on interaction with a '0' interval? That could