search for: haspartialregisterupd

...fully update the > destination's super-register. > > One way to expose this information is (again) via tablegen. For example, we > could add a flag in the tablegen instruction class to tag instructions that > perform partial register updates. Something like this: 'bit > hasPartialRegisterUpdate = 1'. However, this would force a `let > hasPartialRegisterUpdate = 0` on several instruction definitions. > > Another approach is to have a MCSubtargetInfo hook similar to this: > virtual bool updatesSuperRegisters(unsigned short opcode) { return false; } > > Targets...

Hi Andrew, Thanks for the feedback! On Fri, Mar 2, 2018 at 1:16 AM, Andrew Trick <atrick at apple.com> wrote: > > On Mar 1, 2018, at 9:22 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> > wrote: > > Hi all, > > At Sony we developed an LLVM based performance analysis tool named > llvm-mca. We > currently use it internally to statically measure the

...te the > destination's super-register. > > One way to expose this information is (again) via tablegen.  For > example, we > could add a flag in the tablegen instruction class to tag instructions > that > perform partial register updates. Something like this: 'bit > hasPartialRegisterUpdate = 1'. However, this would force a `let > hasPartialRegisterUpdate = 0` on several instruction definitions. > > Another approach is to have a MCSubtargetInfo hook similar to this: >     virtual bool updatesSuperRegisters(unsigned short opcode) { return > false; } > > Tar...

...ly update the > destination's super-register. > > One way to expose this information is (again) via tablegen. For example, > we > could add a flag in the tablegen instruction class to tag instructions that > perform partial register updates. Something like this: 'bit > hasPartialRegisterUpdate = 1'. However, this would force a `let > hasPartialRegisterUpdate = 0` on several instruction definitions. > > Another approach is to have a MCSubtargetInfo hook similar to this: > virtual bool updatesSuperRegisters(unsigned short opcode) { return > false; } > > Targ...

...update, and which instructions fully update the destination's super-register. One way to expose this information is (again) via tablegen. For example, we could add a flag in the tablegen instruction class to tag instructions that perform partial register updates. Something like this: 'bit hasPartialRegisterUpdate = 1'. However, this would force a `let hasPartialRegisterUpdate = 0` on several instruction definitions. Another approach is to have a MCSubtargetInfo hook similar to this: virtual bool updatesSuperRegisters(unsigned short opcode) { return false; } Targets will be able to override this...