Displaying 7 results from an estimated 7 matches for "hasopsize".
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hash_size
2010 Dec 16
1
[LLVMdev] x86 disassembler: if-statement with redundant branch
...ler/X86DisassemblerDecoder.c 2010-12-16 16:24:28.583323293 +0100
@@ -412,11 +412,6 @@
insn->addressSize = (hasAdSize ? 4 : 8);
insn->displacementSize = 4;
insn->immediateSize = 4;
- } else if (insn->rexPrefix) {
- insn->registerSize = (hasOpSize ? 2 : 4);
- insn->addressSize = (hasAdSize ? 4 : 8);
- insn->displacementSize = (hasOpSize ? 2 : 4);
- insn->immediateSize = (hasOpSize ? 2 : 4);
} else {
insn->registerSize = (hasOpSize ? 2 : 4);
insn->addressSize = (hasAd...
2013 Sep 12
1
[LLVMdev] [patch] remove redundant code in X86DisassemblerDecoder.c
...er.c
@@ -550,11 +550,6 @@ static int readPrefixes(struct InternalInstruction*
insn) {
insn->addressSize = (hasAdSize ? 4 : 8);
insn->displacementSize = 4;
insn->immediateSize = 4;
- } else if (insn->rexPrefix) {
- insn->registerSize = (hasOpSize ? 2 : 4);
- insn->addressSize = (hasAdSize ? 4 : 8);
- insn->displacementSize = (hasOpSize ? 2 : 4);
- insn->immediateSize = (hasOpSize ? 2 : 4);
} else {
insn->registerSize = (hasOpSize ? 2 : 4);
insn->addressSize = (hasAd...
2014 Mar 31
2
[LLVMdev] registerSize on X86 confused?
Hi,
In file X86DisassemblerDecoder.c, we have function readPrefixes() with
below code:
.....
} else if (insn->mode == MODE_32BIT) {
insn->registerSize = (hasOpSize ? 2 : 4);
insn->addressSize = (hasAdSize ? 2 : 4);
insn->displacementSize = (hasAdSize ? 2 : 4);
insn->immediateSize = (hasOpSize ? 2 : 4);
}
....
This is confused to me: so we have registerSize to be either 2 or 4 bytes.
But we might have instruction like:...
2014 Apr 02
2
[LLVMdev] registerSize on X86 confused?
...PM, Jun Koi <junkoi2004 at gmail.com> wrote:
>
>> Hi,
>>
>> In file X86DisassemblerDecoder.c, we have function readPrefixes() with
>> below code:
>>
>> .....
>> } else if (insn->mode == MODE_32BIT) {
>> insn->registerSize = (hasOpSize ? 2 : 4);
>> insn->addressSize = (hasAdSize ? 2 : 4);
>> insn->displacementSize = (hasAdSize ? 2 : 4);
>> insn->immediateSize = (hasOpSize ? 2 : 4);
>> }
>> ....
>>
>> This is confused to me: so we have registerSize to b...
2009 Jun 15
0
[LLVMdev] Regular Expressions
On Jun 15, 2009, at 11:33 AM, David Greene wrote:
> To reduce redundancy, developers must be able to write generic
> patterns
> like this:
>
> [(set DSTREGCLASS:$dst, // rr, rrr
> (xor (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src1))),
> (INTSRCTYPE (bitconvert (SRCTYPE SRCREGCLASS:$src2)))))],
>
> The substitution then fills in the appropriate types,
2009 Jun 15
2
[LLVMdev] Regular Expressions
Chris Lattner wrote:
> However, I don't see any reason to base this off of strings. Instead
> of passing down "f32" as a string, why not do something like this
> pseudo code:
>
> class X86ValueType {
> RegisterClass RegClass;
> ...
> }
>
> def X86_f32 : X86ValueType {
> let RegClass = FR32;
> ... };
> def X86_i32 :
2009 Jun 17
3
[LLVMdev] Regular Expressions
...v??", BaseType)).VT,
cast<X86ValueType>(!strconcat("X86v??", BaseType)).RegClass, // Src
cast<X86ValueType>(!strconcat("X86v??", BaseType)).RegClass, // Dst
[and probably some other stuff],
ipatterns,
asm
> {
let Prefix = TA;
let HasOpSize = 1;
let HasVEX = 1;
}
def V#NAME#_128rrm_Int : ...
def V#NAME#_256rrr_Int : ... {
let Prefix = TA;
let HasOpSize = 1;
let HasVEX = 1;
let HasVEX_L = 1;
}
def V#NAME#_256rrm_Int : ...
}
Ok, that's the first level and right here we have a problem. How do we figure...