Displaying 5 results from an estimated 5 matches for "hasclwb".
2018 Mar 18
0
Generating a custom opcode from an LLVM intrinsic
...6Instr*.td you can
find others.
let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
"clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
IIC_SSE_PREFETCH>, PD;
let Predicates = [HasCLWB], SchedRW = [WriteLoad] in
def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src",
[(int_x86_clwb addr:$src)], IIC_SSE_PREFETCH>, PD;
The encoding information for the binary output is buried in these
definitions too. If you tell me what opcode you...
2018 Mar 19
4
Generating a custom opcode from an LLVM intrinsic
...gt;
> let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
> def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
> "clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
> IIC_SSE_PREFETCH>, PD;
>
> let Predicates = [HasCLWB], SchedRW = [WriteLoad] in
> def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src",
> [(int_x86_clwb addr:$src)], IIC_SSE_PREFETCH>, PD;
>
> The encoding information for the binary output is buried in these
> definitions too. If you...
2018 Mar 18
2
Generating a custom opcode from an LLVM intrinsic
Hello all. LLVM newbie here. If anything seems glaringly wrong with my use
of LLVM, that's probably why.
Here's what I'm trying to do. I have modified the gem5 simulator to accept
a "new" x86 instruction. I've done this by just reserving the opcode in
gem5's ISA specification, just as all other instructions are specified.
I'm trying to get an LLVM backend to
2018 Mar 19
0
Generating a custom opcode from an LLVM intrinsic
...tes = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
>> def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
>> "clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
>> IIC_SSE_PREFETCH>, PD;
>>
>> let Predicates = [HasCLWB], SchedRW = [WriteLoad] in
>> def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src",
>> [(int_x86_clwb addr:$src)], IIC_SSE_PREFETCH>, PD;
>>
>> The encoding information for the binary output is buried in these
>> def...
2018 Mar 20
1
Generating a custom opcode from an LLVM intrinsic
...], SchedRW = [WriteLoad] in
>>> def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
>>> "clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
>>> IIC_SSE_PREFETCH>, PD;
>>>
>>> let Predicates = [HasCLWB], SchedRW = [WriteLoad] in
>>> def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src",
>>> [(int_x86_clwb addr:$src)], IIC_SSE_PREFETCH>, PD;
>>>
>>> The encoding information for the binary output is buried in th...