search for: hasaltivec

Displaying 20 results from an estimated 25 matches for "hasaltivec".

[LLVMdev] Getting command line options to affect subtarget features
2013 Jan 31
2
[LLVMdev] Getting command line options to affect subtarget features
...rying to solve: Invoking clang on PowerPC with -fno-altivec has no effect. >From what I've been able to piece together, PPC.td specifies various CPUs and the processor features available on each. So for example we have: def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", "Enable Altivec instructions">; def : Processor<"pwr7", G5Itineraries, [DirectivePwr7, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, Feat...
[LLVMdev] Getting command line options to affect subtarget features
2013 Jan 31
2
[LLVMdev] Getting command line options to affect subtarget features
...ivec has no effect. > > > > From what I've been able to piece together, PPC.td specifies various > > CPUs and the processor features available on each. So for example we > > have: > > > > def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", > > "true", > > "Enable Altivec > > instructions">; > > > > def : Processor<"pwr7", G5Itineraries, > > [DirectivePwr7, Fe...
[LLVMdev] Getting command line options to affect subtarget features
2013 Jan 31
0
[LLVMdev] Getting command line options to affect subtarget features
...on PowerPC with > -fno-altivec has no effect. > > From what I've been able to piece together, PPC.td specifies various > CPUs and the processor features available on each. So for example we > have: > > def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", > "true", > "Enable Altivec > instructions">; > > def : Processor<"pwr7", G5Itineraries, > [DirectivePwr7, FeatureAltivec, >...
[LLVMdev] Getting command line options to affect subtarget features
2013 Jan 31
2
[LLVMdev] Getting command line options to affect subtarget features
...From what I've been able to piece together, PPC.td specifies various > > > > CPUs and the processor features available on each. So for example we > > > > have: > > > > > > > > def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", > > > > "true", > > > > "Enable Altivec > > > > instructions">; > > > > > > > > def : Processor<"pwr7", G5Itinerari...
[LLVMdev] Getting command line options to affect subtarget features
2013 Jan 31
0
[LLVMdev] Getting command line options to affect subtarget features
...> > > > From what I've been able to piece together, PPC.td specifies various > > > CPUs and the processor features available on each. So for example we > > > have: > > > > > > def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", > > > "true", > > > "Enable Altivec > > > instructions">; > > > > > > def : Processor<"pwr7", G5Itineraries, > > >...
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 11
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...> const uint32_t * > PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, > CallingConv::ID CC) const { > const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); > ... > return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask > : CSR_SVR464_RegMask) > : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask > : CSR_SVR432_RegMask); > } > > In any case, the...
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 11
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...> const uint32_t * > PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, > CallingConv::ID CC) const { > const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); > ... > return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask > : CSR_SVR464_RegMask) > : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask > : CSR_SVR432_RegMask); > } > > In any case, the...
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 18
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...> const uint32_t * > PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, > CallingConv::ID CC) const { > const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); > ... > return TM.isPPC64() ? (Subtarget.hasAltivec() ? > CSR_SVR464_Altivec_RegMask > : CSR_SVR464_RegMask) > : (Subtarget.hasAltivec() ? > CSR_SVR432_Altivec_RegMask > : CSR_SVR432_RegMask); > } > > In any c...
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 11
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...> const PPCSubtarget &Subtarget = > > > > > MF.getSubtarget<PPCSubtarget>(); > > > > > > > > > > > > > > > ... > > > > > > > > > > > > > > > return TM.isPPC64() ? (Subtarget.hasAltivec() ? > > > > > CSR_SVR464_Altivec_RegMask > > > > > > > > > > > > > > > : CSR_SVR464_RegMask) > > > > > > > > > > > > > > > : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask > &gt...
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 18
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...* >> PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, >> CallingConv::ID CC) const { >> const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); >> ... >> return TM.isPPC64() ? (Subtarget.hasAltivec() ? >> CSR_SVR464_Altivec_RegMask >> : CSR_SVR464_RegMask) >> : (Subtarget.hasAltivec() ? >> CSR_SVR432_Altivec_RegMask >> : CSR_SVR432_RegMask); >&...
[LLVMdev] Getting command line options to affect subtarget features
2013 Jan 31
0
[LLVMdev] Getting command line options to affect subtarget features
...been able to piece together, PPC.td specifies various > > > > > CPUs and the processor features available on each. So for example we > > > > > have: > > > > > > > > > > def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", > > > > > "true", > > > > > "Enable Altivec > > > > > instructions">; > > > > > > > > > > def : Processor<&quo...
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 11
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
*Vivek Pandya* On Wed, May 11, 2016 at 10:02 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > *Vivek Pandya* > > > On Wed, May 11, 2016 at 9:43 AM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> >> On May 10, 2016, at 6:06 PM, Hal Finkel <hfinkel at anl.gov> wrote: >> >> >> >>
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 18
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...* >> PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, >> CallingConv::ID CC) const { >> const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); >> ... >> return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask >> : CSR_SVR464_RegMask) >> : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask >> : CSR_SVR432_RegMask); >> } >> &g...
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 24
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...gisterInfo::getCallPreservedMask(const MachineFunction &MF, >>> CallingConv::ID CC) const { >>> const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); >>> ... >>> return TM.isPPC64() ? (Subtarget.hasAltivec() ? >>> CSR_SVR464_Altivec_RegMask >>> : CSR_SVR464_RegMask) >>> : (Subtarget.hasAltivec() ? >>> CSR_SVR432_Altivec_RegMask >>> : CSR_SV...
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 24
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...gt; MF.getSubtarget<PPCSubtarget>(); > > > > > > > > > > > > > > > > > > > > > ... > > > > > > > > > > > > > > > > > > > > > return TM.isPPC64() ? (Subtarget.hasAltivec() ? > > > > > > CSR_SVR464_Altivec_RegMask > > > > > > > > > > > > > > > > > > > > > : CSR_SVR464_RegMask) > > > > > > > > > > > > > > > > > > > > &...
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...allPreservedMask(const MachineFunction &MF, >>>> CallingConv::ID CC) const { >>>> const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); >>>> ... >>>> return TM.isPPC64() ? (Subtarget.hasAltivec() ? >>>> CSR_SVR464_Altivec_RegMask >>>> : CSR_SVR464_RegMask) >>>> : (Subtarget.hasAltivec() ? >>>> CSR_SVR432_Altivec_RegMask >>>>...
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...; > > > > > > > > > > > > > > ... > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > return TM.isPPC64() ? (Subtarget.hasAltivec() ? > > > > > > > > CSR_SVR464_Altivec_RegMask > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > : CSR_SVR464_RegMask) > > > >...
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...(const MachineFunction &MF, >>>>> CallingConv::ID CC) const { >>>>> const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); >>>>> ... >>>>> return TM.isPPC64() ? (Subtarget.hasAltivec() ? >>>>> CSR_SVR464_Altivec_RegMask >>>>> : CSR_SVR464_RegMask) >>>>> : (Subtarget.hasAltivec() ? >>>>> CSR_SVR432_Altivec_RegMask >>>>>...
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...nction &MF, >>>>>> CallingConv::ID CC) const { >>>>>> const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); >>>>>> ... >>>>>> return TM.isPPC64() ? (Subtarget.hasAltivec() ? >>>>>> CSR_SVR464_Altivec_RegMask >>>>>> : CSR_SVR464_RegMask) >>>>>> : (Subtarget.hasAltivec() ? >>>>>> CSR_SVR432_Altivec_RegMask >>>>>&...
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
...> const uint32_t * > PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, > CallingConv::ID CC) const { > const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); > ... > return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask > : CSR_SVR464_RegMask) > : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask > : CSR_SVR432_RegMask); > } > > In any case, the...