Displaying 8 results from an estimated 8 matches for "hardware_".
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hardware
2010 Nov 26
4
[LLVMdev] LLVMdev Digest, Vol 77, Issue 41
...st not be optimized as integers - eg if two saturated fixed point constants would overflow in an addition operation, the result should as well be saturated. Doing this in a series of steps with intrinsics would be quite ridiculous as far as performance goes, because this is _supported by the DSP in hardware_ in a single instruction :-)
What about perhaps introducing a new type, and allowing just minor extensions, while barring it from more heavy scattered code? I mean, the GVN pass works by just adding an enum entry and a switch case for each new instruction. But in other cases, there are more LOCs i...
2010 Nov 27
0
[LLVMdev] LLVMdev Digest, Vol 77, Issue 41
...integers - eg if two saturated fixed point constants would overflow in
> an addition operation, the result should as
> well be saturated. Doing this in a series of steps with intrinsics would
> be quite ridiculous as far as performance goes,
> because this is _supported by the DSP in hardware_ in a single instruction
> :-)
Isn't it better to add instructions for saturated and/or fixed point
arithmetic? ... At least that would be consistent with the design of having
separate instructions for signed and unsigned add etc.
- Morten
2010 Nov 29
2
[LLVMdev] Fw: LLVMdev Digest, Vol 77, Issue 41
...> > two saturated fixed point constants would overflow in an addition
> > operation, the result should as well be saturated. Doing this in a
> > series of steps with intrinsics would be quite ridiculous as far as
> > performance goes, because this is _supported by the DSP in hardware_
> > in a single instruction :-)
> >
> > What about perhaps introducing a new type, and allowing just minor
> > extensions, while barring it from more heavy scattered code? I mean,
> > the GVN pass works by just adding an enum entry and a switch case
> > for eac...
2010 Nov 26
0
[LLVMdev] LLVMdev Digest, Vol 77, Issue 41
...as integers - eg if
> two saturated fixed point constants would overflow in an addition
> operation, the result should as well be saturated. Doing this in a
> series of steps with intrinsics would be quite ridiculous as far as
> performance goes, because this is _supported by the DSP in hardware_
> in a single instruction :-)
>
> What about perhaps introducing a new type, and allowing just minor
> extensions, while barring it from more heavy scattered code? I mean,
> the GVN pass works by just adding an enum entry and a switch case for
> each new instruction. But in othe...
2010 Nov 29
2
[LLVMdev] fixed point types
...two saturated fixed point constants would overflow in an addition
>>> operation, the result should as well be saturated. Doing this in a
>>> series of steps with intrinsics would be quite ridiculous as far as
>>> performance goes, because this is _supported by the DSP in hardware_
>>> in a single instruction :-)
>>>
>>> What about perhaps introducing a new type, and allowing just minor
>>> extensions, while barring it from more heavy scattered code? I mean,
>>> the GVN pass works by just adding an enum entry and a switch case
&g...
2016 Jun 13
2
[Proposal][RFC] Cache aware Loop Cost Analysis
...> patches on it.
>
> Yes, this sounds like the right direction. The targets obviously need to
> provide this information.
>
I'd like to help review this as it'll be necessary to implement
http://wg21.link/p0154r1 which is (likely) in C++17. It adds two
values, constexpr
std::hardware_{constructive,destructive}_interference_size, because in some
configurations you don't have a precise cacheline size but rather a range
based on what multiple architectures have implemented for the same ISA. I
think you'll want something similar.
-------------- next part --------------
An HT...
2010 Nov 30
0
[LLVMdev] fixed point types
...fixed point constants would overflow in an addition
> >>> operation, the result should as well be saturated. Doing this in a
> >>> series of steps with intrinsics would be quite ridiculous as far as
> >>> performance goes, because this is _supported by the DSP in hardware_
> >>> in a single instruction :-)
> >>>
> >>> What about perhaps introducing a new type, and allowing just minor
> >>> extensions, while barring it from more heavy scattered code? I mean,
> >>> the GVN pass works by just adding an enum e...
2016 Jun 08
5
[Proposal][RFC] Cache aware Loop Cost Analysis
Hi,
This is a proposal about implementing an analysis that calculates loop cost
based on cache data. The primary motivation for implementing this is to
write profitability measures for cache related optimizations like
interchange, fusion, fission, pre-fetching and others.
I have implemented a prototypical version at http://reviews.llvm.org/D21124.
The patch basically creates groups of references