search for: hardbound

Displaying 10 results from an estimated 10 matches for "hardbound".

2013 Sep 10
3
[LLVMdev] Intel Memory Protection Extensions (and types question)
...in BNDx registers. --kcc > > >> The pointer and metadata exist in separate registers, but single > instructions (loads and stores) operate on the pointer + metadata. > > Which MPX instructions do you mean here? > > Ah, sorry, I was confusing MPX with one of the other HardBound-like > schemes here. In MPX, you must implicitly insert the BNDCU and BNDCL > instructions. I would expect that you'd want to model the BNDCU + BNDCL + > MOV sequence as a single pseudo for as long as possible to ensure that the > bounds checks were performed at the correct time a...
2013 Sep 10
0
[LLVMdev] Intel Memory Protection Extensions (and types question)
...3, at 12:13, Kostya Serebryany <kcc at google.com> wrote: > Well, ok, you can treat this as a 192-bit fat pointer, but AFAICT this is not the real intention of the MPX developers > since a fat pointer will break all ABIs, and MPX tries to preserve them. MPX is an implementation of the HardBound concept from UPenn, where this was a design goal (see also their 'low-fat pointers' work). > I don't think we need fat pointers to support MPX in LLVM -- it will complicate the implementation beyond necessity. (My 2c) Fat pointers, however, are required for other architectures (i...
2019 Nov 09
2
Need help modding src.rpms to generate complete SAMBA AD DC binary RPMs for CentOS 8
...a-dc binary rpm has been disabled for rhel family builds. Apparently Red Hat does not want to support a unified SAMBA AD DC environment. I believe we have all of the componentns needed to set up a fully up-to-date samba-dc binary. But it's been decades since I last rolled up my sleeves with my hardbound copy of "Maximum RPM" and built custom binary rpms. Has anyone already done this as a COPR or similar project? Failing that, I'm willing to work with anyone with more up-to-date rpmbuild tools to create and document the process. --Doc Savage Fairview Heights, IL
2016 Jan 28
2
Intel MPX support (instrumentation pass similar to gcc's Pointer Checker)
...instructions). I wonder if anyone is currently working on the LLVM pass for MPX instrumentation, similar to Pointer Checker in gcc. If yes, could anyone elaborate on the status and accessability to other researchers? And if any help is needed? Prof. Santosh Nagarakatte, the author of SoftBound/HardBound/WatchDog Lite, answered that he is not currently involved in MPX. But he pointed to the SoftBoundCETS prototype at https://github.com/santoshn/softboundcets-34 . Therefore, I was thinking about adapting SoftBound to MPX, as a drop-in replacement for gcc's PointerChecker. Cou...
2013 Sep 10
0
[LLVMdev] Intel Memory Protection Extensions (and types question)
...checking in a similar way to the Thumb-2EE extensions. >> The pointer and metadata exist in separate registers, but single instructions (loads and stores) operate on the pointer + metadata. > Which MPX instructions do you mean here? Ah, sorry, I was confusing MPX with one of the other HardBound-like schemes here. In MPX, you must implicitly insert the BNDCU and BNDCL instructions. I would expect that you'd want to model the BNDCU + BNDCL + MOV sequence as a single pseudo for as long as possible to ensure that the bounds checks were performed at the correct time and not elided, but t...
2013 Sep 10
2
[LLVMdev] Intel Memory Protection Extensions (and types question)
On Tue, Sep 10, 2013 at 1:19 PM, David Chisnall <David.Chisnall at cl.cam.ac.uk > wrote: > On 10 Sep 2013, at 10:13, Kostya Serebryany <kcc at google.com> wrote: > > > How did you come with 320 bits? > > 320=64*4+64, which is the size of the metadata table entry plus pointer > size, > > > Sorry, that should have been 192. The specification allows the
2011 Aug 17
10
cluster.min-free-disk separate for each, brick
On 15/08/11 20:00, gluster-users-request at gluster.org wrote: > Message: 1 > Date: Sun, 14 Aug 2011 23:24:46 +0300 > From: "Deyan Chepishev - SuperHosting.BG"<dchepishev at superhosting.bg> > Subject: [Gluster-users] cluster.min-free-disk separate for each > brick > To: gluster-users at gluster.org > Message-ID:<4E482F0E.3030604 at
2013 Sep 10
0
[LLVMdev] Intel Memory Protection Extensions (and types question)
...f a pointer is not always log2() of its addressable range - There are some registers that either only store pointers or only store pointer metadata - Loads and stores of pointers may need to be treated differently to loads and stores of data I believe that our case and MPX (which is quite close to HardBounds) are close to being opposite end of the spectrum, so it would be nice if we could come up with a generic design that can support both, as it would then simplify life for any future architectures that have this support. In our case: - Fat pointers are 256 bits - The metadata is stored alongside t...
2013 Sep 09
4
[LLVMdev] Intel Memory Protection Extensions (and types question)
Hi all, I'm currently adding new instructions and registers to the X86 code generator for Intel Memory Protection Extensions [1]. A class of special-purpose registers BNDx each holds 2 x 64-bit values. The components are not individually readable or writable (except by going through memory) but there are instructions that read only one of the two elements. The two 64-bit values can be
2013 Sep 10
2
[LLVMdev] Intel Memory Protection Extensions (and types question)
...f its addressable > range > - There are some registers that either only store pointers or only store > pointer metadata > - Loads and stores of pointers may need to be treated differently to loads > and stores of data > > I believe that our case and MPX (which is quite close to HardBounds) are > close to being opposite end of the spectrum, so it would be nice if we > could come up with a generic design that can support both, as it would then > simplify life for any future architectures that have this support. In our > case: > > - Fat pointers are 256 bits > -...