Displaying 7 results from an estimated 7 matches for "handleregisterdef".
2007 Apr 03
2
[LLVMdev] Live intervals and aliasing registers problem
...x8503c80, LLVM BB @0x8501af0, ID#0):
Live Ins: %R0 %R1
%reg1024 = ORI %R0<kill>, 0
%reg1025 = ORI %R1<kill>, 0
V4R0 is getting killed because handleLiveInRegister() is called on
all results of getAliasSet() for each of the liveins (this is in
LiveIntervals::computeIntervals() ).
handleRegisterDef() does a similar thing where calls
handlePhysicalRegisterDef() on all members of getAliasSet() returned
for the def, which also triggers this problem.
Is it calling handle*() on the alias set of a register thats the
culprit, or is it some mishandling in KillsRegister()?
Thanks
--
Christophe...
2007 Apr 04
0
[LLVMdev] Live intervals and aliasing registers problem
...t; Live Ins: %R0 %R1
> %reg1024 = ORI %R0<kill>, 0
> %reg1025 = ORI %R1<kill>, 0
>
> V4R0 is getting killed because handleLiveInRegister() is called on
> all results of getAliasSet() for each of the liveins (this is in
> LiveIntervals::computeIntervals() ).
>
> handleRegisterDef() does a similar thing where calls
> handlePhysicalRegisterDef() on all members of getAliasSet() returned
> for the def, which also triggers this problem.
>
> Is it calling handle*() on the alias set of a register thats the
> culprit, or is it some mishandling in KillsRegister()?
Th...
2010 May 18
3
[LLVMdev] selection dag speedups / llc speedups
...hg 0x0000000000886426
llvm::LiveIntervals::handleVirtualRegisterDef(llvm::MachineBasicBlock*,
llvm::ilist_iterator<llvm::MachineInstr>, llvm::SlotIndex,
llvm::MachineOperand&, unsigned int, llvm::LiveInterval&) + 3910
7 llc.hg 0x0000000000888429
llvm::LiveIntervals::handleRegisterDef(llvm::MachineBasicBlock*,
llvm::ilist_iterator<llvm::MachineInstr>, llvm::SlotIndex,
llvm::MachineOperand&, unsigned int) + 409
8 llc.hg 0x000000000088ade0
llvm::LiveIntervals::computeIntervals() + 2496
9 llc.hg 0x000000000088b56f
llvm::LiveIntervals::runOnMachineFunct...
2010 May 18
0
[LLVMdev] selection dag speedups / llc speedups
On May 17, 2010, at 9:09 PM, Rafael Espindola wrote:
>> The fast and local register allocators are meant to be used on unoptimized code, a 'Debug build'. While they do work on optimized code, they do not give good results. Their primary goal is compile time, not code quality.
>
> Yes, we have a somewhat uncommon use case. It is fine to spend time
> optimizing bitcode (LTO
2010 May 18
2
[LLVMdev] selection dag speedups / llc speedups
> The fast and local register allocators are meant to be used on unoptimized code, a 'Debug build'. While they do work on optimized code, they do not give good results. Their primary goal is compile time, not code quality.
Yes, we have a somewhat uncommon use case. It is fine to spend time
optimizing bitcode (LTO is a OK), but we want to make the final IL ->
Executable translation
2007 Mar 27
0
[LLVMdev] Live intervals and aliasing registers problem
On Mar 25, 2007, at 7:12 AM, Christopher Lamb wrote:
> While beginning to add vector registers to a back end I came across
> the following problem: as soon as I define two sets of registers
> that have a many-to-one mapping the live interval pass appears to
> double-kill the mapped-onto register. I have the following excerpts
> from my RegisterInfo.td.
>
> def V4R0
2007 Mar 25
2
[LLVMdev] Live intervals and aliasing registers problem
While beginning to add vector registers to a back end I came across
the following problem: as soon as I define two sets of registers that
have a many-to-one mapping the live interval pass appears to double-
kill the mapped-onto register. I have the following excerpts from my
RegisterInfo.td.
def V4R0 : R4v<0 , "V4R0 ", []>, DwarfRegNum<0>;
def R0 : Rg<0 ,