search for: handlephysicalregisterdef

...e A to Z because of the overlap! > The second loop might have a comment like: > > // If the register is not dead at the defining instruction, it must be used > // and killed by some subsequent instruction. Find that instruction now, which > // always exists I added comments to the handlePhysicalRegisterDef. Let me know if it makes more sense now. > Finally, why I've started all this. I forgot to add machine CFG edge and got > misterious crash. I've applied the attached patch, which checks that all > basic blocks are reachable from function entry. Any comments on: > > - whet...

I've just spend some time looking at the above function, and while I understood what it does, a comment would have helped a lot. Maybe, something like: // Determine the end of the live interval for this register // For physical register, all internvals are within basic blocks so // we look for the instruction in this basic block which last uses it. The first loop might have a comment like:

...%reg1024 = ORI %R0<kill>, 0 %reg1025 = ORI %R1<kill>, 0 V4R0 is getting killed because handleLiveInRegister() is called on all results of getAliasSet() for each of the liveins (this is in LiveIntervals::computeIntervals() ). handleRegisterDef() does a similar thing where calls handlePhysicalRegisterDef() on all members of getAliasSet() returned for the def, which also triggers this problem. Is it calling handle*() on the alias set of a register thats the culprit, or is it some mishandling in KillsRegister()? Thanks -- Christopher Lamb

...those functions just enabled other passes to start moving the blocks around, and that seems to have exposed problems of its own. For example, sometimes LiveIntervals asserts with: register: %CTR8 clang: /llvm-trunk/lib/CodeGen/LiveIntervalAnalysis.cpp:446: void llvm::LiveInterval s::handlePhysicalRegisterDef(llvm::MachineBasicBlock*, llvm::MachineBasicBlock::iterator, llvm::SlotIndex, llvm::MachineOperand&, llvm::LiveInt erval&): Assertion `!isAllocatable(interval.reg) && "Physregs shouldn't be live out!"' failed. in this case the loop is quite simple: 944B BB#8: d...

...0 > %reg1025 = ORI %R1<kill>, 0 > > V4R0 is getting killed because handleLiveInRegister() is called on > all results of getAliasSet() for each of the liveins (this is in > LiveIntervals::computeIntervals() ). > > handleRegisterDef() does a similar thing where calls > handlePhysicalRegisterDef() on all members of getAliasSet() returned > for the def, which also triggers this problem. > > Is it calling handle*() on the alias set of a register thats the > culprit, or is it some mishandling in KillsRegister()? This is a pretty serious bug. LiveVariables::KillsRegister should no...

On Jun 7, 2012, at 10:54 PM, Hal Finkel wrote: > For example, sometimes LiveIntervals asserts with: > register: > %CTR8 > clang: /llvm-trunk/lib/CodeGen/LiveIntervalAnalysis.cpp:446: > void llvm::LiveInterval > s::handlePhysicalRegisterDef(llvm::MachineBasicBlock*, > llvm::MachineBasicBlock::iterator, llvm::SlotIndex, > llvm::MachineOperand&, llvm::LiveInt erval&): Assertion > `!isAllocatable(interval.reg) && "Physregs shouldn't be live out!"' > failed. When machine code is still in SSA...

...nfo.td) I run into // The only case we should have a dead physreg here without a killing or // instruction where we know it's dead is if it is live-in to the function // and never used. assert(!CopyMI && "physreg was not killed in defining block!"); in LiveIntervals::handlePhysicalRegisterDef(). The dump() of the MBB from the debugger looks like the following: entry.ifcont267_crit_edge: 0x12bc368, LLVM BB @0x12bb900, ID#2: Predecessors according to CFG: 0x12bc290 (#0) 0x12bca70 (#1) %reg1033<def> = addC %reg1025<kill>, 0, %CCFLAGS<imp-def,dead> %r...

...ote: > > On Jun 7, 2012, at 10:54 PM, Hal Finkel wrote: > > > For example, sometimes LiveIntervals asserts with: > > register: > > %CTR8 > > clang: /llvm-trunk/lib/CodeGen/LiveIntervalAnalysis.cpp:446: > > void llvm::LiveInterval > > s::handlePhysicalRegisterDef(llvm::MachineBasicBlock*, > > llvm::MachineBasicBlock::iterator, llvm::SlotIndex, > > llvm::MachineOperand&, llvm::LiveInt erval&): Assertion > > `!isAllocatable(interval.reg) && "Physregs shouldn't be live out!"' > > failed. FYI: I just co...

...ase we should have a dead physreg here without a > killing or > // instruction where we know it's dead is if it is live-in to the > function > // and never used. > assert(!CopyMI && "physreg was not killed in defining block!"); > > in LiveIntervals::handlePhysicalRegisterDef(). > > The dump() of the MBB from the debugger looks like the following: > > entry.ifcont267_crit_edge: 0x12bc368, LLVM BB @0x12bb900, ID#2: > Predecessors according to CFG: 0x12bc290 (#0) 0x12bca70 (#1) > %reg1033<def> = addC %reg1025<kill>, 0, %CCFLAGS<i...

On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote: > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN > Predecessors according to CFG: BB#0 BB#1 > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 > %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12 > %vreg13<def> = BDNZ8 %vreg13,

On Mar 25, 2007, at 7:12 AM, Christopher Lamb wrote: > While beginning to add vector registers to a back end I came across > the following problem: as soon as I define two sets of registers > that have a many-to-one mapping the live interval pass appears to > double-kill the mapped-onto register. I have the following excerpts > from my RegisterInfo.td. > > def V4R0

While beginning to add vector registers to a back end I came across the following problem: as soon as I define two sets of registers that have a many-to-one mapping the live interval pass appears to double- kill the mapped-onto register. I have the following excerpts from my RegisterInfo.td. def V4R0 : R4v<0 , "V4R0 ", []>, DwarfRegNum<0>; def R0 : Rg<0 ,

Hello again, I am trying to implement an optimization pass for PowerPC such that simple loops use the special "counter register" (CTR) to track the induction variable. This is helpful because, in addition to reducing register pressure, there is a combined decrement-compare-and-branch instruction BZND (there are also other related instructions). I started this process by converting the