search for: handlenode

Displaying 5 results from an estimated 5 matches for "handlenode".

2011 Aug 25
0
[LLVMdev] [RFC] Splitting init.trampoline into init.trampoline and adjust.trampoline
...ches is not that great (since things won't always work, in fact not even compile I think, with not all patches applied). Some minor comments below. > --- a/include/llvm/CodeGen/ISDOpcodes.h > +++ b/include/llvm/CodeGen/ISDOpcodes.h > @@ -566,14 +566,18 @@ namespace ISD { > // HANDLENODE node - Used as a handle for various purposes. > HANDLENODE, > > - // TRAMPOLINE - This corresponds to the init_trampoline intrinsic. > - // It takes as input a token chain, the pointer to the trampoline, > - // the pointer to the nested function, the pointer to pass for...
2011 Aug 23
2
[LLVMdev] [RFC] Splitting init.trampoline into init.trampoline and adjust.trampoline
Hi! Attached set of patches splits llvm.init.trampoline into an "init" phase and an "adjust" phase, as discussed on the "Go on dragonegg" thread. Thanks! -- Sanjoy Das http://playingwithpointers.com -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Split-intrinsics-and-DAG-nodes.patch Type: text/x-diff Size: 8808 bytes Desc:
2013 Mar 19
0
[LLVMdev] setCC and brcond
...addr]> [ORD=1] [ID=0] Legally typed node: 0x17f8f30: i1 = setcc 0x17f6780, 0x17f6980, 0x17f8e30 [ID=0] Legally typed node: 0x17f7280: ch = brcond 0x17f6b80, 0x17f8f30, 0x17f7180 [ID=0] Legally typed node: 0x17f7480: ch = br 0x17f7280, 0x17f7380 [ID=0] Legally typed node: 0x7fff9df7bd30: ch = handlenode 0x17f7480 [ID=0] Type-legalized selection DAG: BB#0 'isZero:entry' SelectionDAG has 13 nodes: 0x17d0fb0: ch = EntryToken [ORD=1] [ID=-3] 0x17d0fb0: <multiple use> 0x17f6680: i32 = Register %vreg0 [ORD=1] [ID=-3] 0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=...
2017 Jul 07
2
Error in v64i32 type in x86 backend
Have you read http://llvm.org/docs/WritingAnLLVMBackend.html and http://llvm.org/docs/CodeGenerator.html ? http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector describes how to define a store instruction. -Eli On 7/6/2017 6:51 PM, hameeza ahmed via llvm-dev wrote: > Please correct me i m stuck at this point. > > On Jul 6, 2017 5:18 PM, "hameeza ahmed"
2017 Jul 07
2
Error in v64i32 type in x86 backend
...:min.iters.checked' SelectionDAG has 1 nodes: t0: ch = EntryToken Combining: t0: ch = EntryToken Optimized lowered selection DAG: BB#0 'foo:min.iters.checked' SelectionDAG has 1 nodes: t0: ch = EntryToken Legally typed node: t0: ch = EntryToken Legally typed node: t65535: ch = handlenode t0 Type-legalized selection DAG: BB#0 'foo:min.iters.checked' SelectionDAG has 1 nodes: t0: ch = EntryToken Legalizing: t0: ch = EntryToken Legalized selection DAG: BB#0 'foo:min.iters.checked' SelectionDAG has 1 nodes: t0: ch = EntryToken Legalizing: t0: ch = EntryToken...