Displaying 20 results from an estimated 128 matches for "hameeza".
2017 Aug 07
3
VBROADCAST Implementation Issues
...perands for MRMSrcMemFrm"' failed.
On Mon, Aug 7, 2017 at 8:23 PM, Craig Topper <craig.topper at gmail.com> wrote:
> masked_gather takes 3 inputs. not just an address. See the AVX512 pattern
> is pasted earlier
>
> ~Craig
>
> On Mon, Aug 7, 2017 at 1:54 AM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> Changed it to;
>>
>> def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst, VK64:$mask),
>> (ins i2048mem:$src),
>> "GATHER_256B\t{$src, {$dst}{${mask}}|${dst}
>> {${mask}}, $...
2019 Apr 23
5
StringRef Iterator Variable Display
Hello,
I want to display the variable names in stringref iterator. But it is not
displayed using following code.
for (set<StringRef>::iterator sit = L.begin(); sit != L.end(); sit++) {
errs() << *sit << " ";
}
How to do this?
Please help..
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2017 Aug 07
2
VBROADCAST Implementation Issues
...t; [(set _.RC:$dst, _.KRCWM:$mask_wb,
> (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
> vectoraddr:$src2))]>, EVEX, EVEX_K,
> EVEX_CD8<_.EltSize, CD8VT1>;
> }
>
> ~Craig
>
> On Sun, Aug 6, 2017 at 2:21 PM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> i want to implement gather for v64i32. i wrote following code.
>>
>> def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst), (ins
>> i2048mem:$src),
>> "GATHER_256B\t{$src, $dst|$ds...
2017 Aug 06
2
VBROADCAST Implementation Issues
.../utils/TableGen/CodeGenDAGPatterns.cpp:2134:
llvm::TreePatternNode *llvm::TreePattern::ParseTreePattern(llvm::Init *,
llvm::StringRef): Assertion `New->getNumTypes() == 1 && "FIXME: Unhandled"'
failed.
What is my mistake?
Please help me.
On Mon, Aug 7, 2017 at 12:03 AM, hameeza ahmed <hahmed2305 at gmail.com> wrote:
> I am trying to implement vector shuffle for v64i32. Is the following
> correct?
>
>
> def VSHUFFLE_256B : I<0xE8, MRMDestReg, (outs VR_2048:$dst),
> (ins VR_2048:$src1, VRPIM_2048:$src2),"VSHUFFLE_256B\t{$src1, $src2,
> $...
2017 Jul 01
2
Jacobi 5 Point Stencil Code not Vectorizing
...i = 1; i <= N-2; i++)
for (j = 1; j <= N-2; j++)
b[i][j] = 0.25 * (a[i][j] + a[i-1][j] + a[i+1][j] + a[i][j-1] +
a[i][j+1]);
for (i = 1; i <= N-2; i++)
for (j = 1; j <= N-2; j++)
a[i][j] = b[i][j];
}
}
I removed restrict over here.
On Sun, Jul 2, 2017 at 3:11 AM, hameeza ahmed <hahmed2305 at gmail.com> wrote:
> further i modified the code to the following;
>
> #include <stdio.h>
> #define N 100351
>
> // This function computes 2D-5 point Jacobi stencil
> void stencil(int a[restrict][N], int b[restrict][N])
> {
> int i, j,...
2017 Jul 08
5
Error in v64i32 type in x86 backend
...gmail.com>
wrote:
> Yes its an opcode conflict. You'll have to look through Intel documents
> and find an unused opcode. I've only added instructions based on a real
> spec so I don't know how to make up an opcode.
>
> ~Craig
>
> On Fri, Jul 7, 2017 at 10:43 PM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> Thank You.
>>
>> Now i am getting this error repeatedly;
>>
>> Error: Primary decode conflict: VADD_256B would overwrite INC8r
>> ModRM 192
>> Opcode 254
>> Context IC
>> Error: Primar...
2017 Jul 14
3
error:Ran out of lanemask bits to represent subregister
Do your 32768 registers also have sub registers?
I can't tell you exactly what to change. I'm not familiar with the code. I
would just be running grep or something.
~Craig
On Fri, Jul 14, 2017 at 10:23 AM, hameeza ahmed <hahmed2305 at gmail.com>
wrote:
> Thank you so much. I think there is no issue with my definitions since i
> have to use larger registers i.e 65536 bit register made from 2 32768
> registers.
> I have seen your mentioned code files. But it looks difficult what to
> chan...
2017 Sep 05
2
Issues in Vector Add Instruction Machine Code Emission
...at 5:45 AM, Craig Topper <craig.topper at gmail.com> wrote:
> Put the TA's back. EVEX/EVEX_4V does not replace TA. They are for
> different things. An EVEX/EVEX_4V instruction must use one of T8, TA, XOP8,
> XOP9, XOPA.
>
> ~Craig
>
> On Mon, Sep 4, 2017 at 5:33 PM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> Thank You,
>> I changed TA to EVEX or EVEX_4V. But now i am getting following error:
>>
>> Invalid prefix!
>> UNREACHABLE executed at /lib/Target/X86/MCTargetDesc/X
>> 86MCCodeEmitter.cpp:647!
>>
>...
2017 Jul 12
2
Using new types v32f32, v32f64 in llvm backend not possible
...sets to the
same instruction based on the vector width/ no of iterations.
I have tried several alternatives but could not succeed.
Also I have asked this question many times but no one responds.
Is there something wrong with this??
Kindly guide me.
Thank You
On Wed, Jul 12, 2017 at 12:56 AM, hameeza ahmed <hahmed2305 at gmail.com>
wrote:
> here by the ********my backend supports v64i32 i mean my hardware.
>
> On Wed, Jul 12, 2017 at 12:49 AM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> Thank you so much. it run fine.
>> Can you please resolve...
2017 Sep 05
2
Issues in Vector Add Instruction Machine Code Emission
...t; cannot because they don't have 2 sources.
>
> What do you intend to do with the binary output once you have it? You
> don't seem to be targeting a particular binary definition so its
> effectively just random numbers.
>
> ~Craig
>
> On Mon, Sep 4, 2017 at 4:28 PM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> Thank You.
>>
>> I used EVEX_4V with all the instructions. I replaced TA and EVEX both
>> with EVEX_4V. Now, I am getting following error:
>>
>> llvm-tblgen: /utils/TableGen/X86RecognizableInstr.cpp:687: v...
2017 Jul 07
2
Error in v64i32 type in x86 backend
Thank You.
On Fri, Jul 7, 2017 at 10:03 AM, Craig Topper <craig.topper at gmail.com>
wrote:
> Yes, that error is from instruction selection. I think your legalization
> changes worked fine.
>
> ~Craig
>
> On Thu, Jul 6, 2017 at 8:21 PM, hameeza ahmed via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> also i further run the following command;
>> llc -debug filer-knl_o3.ll
>>
>> and its output is attached here. by looking at the output can we say that
>> legalization runs fine and the error is...
2018 Jul 24
2
KNL Vectorization with larger vector width
...=63 and I
set vector width=64, no vector instructions are emitted. it should do as
previous and gives <32xi32> and <16xi32> vector instructions.
How to do this?
What adjustments are needed?
Please help
I m trying this but unable to solve.
Thank You
On Tue, Jul 24, 2018 at 4:44 PM, hameeza ahmed <hahmed2305 at gmail.com> wrote:
> Hello,
> Do i need to change following function;
>
> unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) {
> if (Vector && !ST->hasSSE1())
> return 0;
>
> if (ST->is64Bit()) {
> if (Vector &&...
2017 Jul 01
3
Jacobi 5 Point Stencil Code not Vectorizing
Does it happen due to loop carried dependence? if yes what is the solution
to vectorize such codes?
please reply. i m waiting.
On Jul 1, 2017 12:30 PM, "hameeza ahmed" <hahmed2305 at gmail.com> wrote:
> I even tried polly but still my llvm IR does not contain vector
> instructions. i used the following command;
>
> clang -S -emit-llvm stencil.c -march=knl -O3 -mllvm -polly -mllvm
> -polly-vectorizer=stripmine -o stencil_poly.ll...
2017 Sep 04
2
Issues in Vector Add Instruction Machine Code Emission
...e encoder assumes that the destination and one of
> the sources must be the same physical register.
>
> TA indicates which of the opcode maps the instruction belongs to. This
> corresponds to encoding 0x3 of the VEX.mmmmm field.
>
> ~Craig
>
> On Mon, Sep 4, 2017 at 4:01 PM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> Sorry to ask but what does it mean to put both?
>>
>> On Tue, Sep 5, 2017 at 4:01 AM, Craig Topper <craig.topper at gmail.com>
>> wrote:
>>
>>> Leave TA. Put both.
>>>
>>> ~Craig...
2017 Aug 17
2
unable to emit vectorized code in LLVM IR
...evable through JIT?
On Fri, Aug 18, 2017 at 12:17 AM, Craig Topper <craig.topper at gmail.com>
wrote:
> What was your lli command line? Is this based on your code where you
> created 2048-bit instructions in the x86 backend?
>
> ~Craig
>
> On Thu, Aug 17, 2017 at 12:12 PM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> Ok. I have managed to vectorize the second loop in the following code.
>> But the first loop is still not vectorized? Why?
>>
>> int main(int argc, char** argv) {
>> int a[1000], b[1000], c[1000]; int g=0;
>&...
2017 Jul 19
2
error:Ran out of lanemask bits to represent subregisterr
...ype. Most of the
> functionality is already localized to the header file, the only exception
> may be the "getAsInteger" function. It shouldn't be too hard to fix up the
> uses to deal with a different underlying type.
>
> -Krzysztof
>
>
> On 7/19/2017 2:56 PM, hameeza ahmed wrote:
>
>> As you mentioned i changed 32 to 64 but now some new errors come which
>> require to change unsigned to uint64_t in mentioned files. i have changed
>> in mentioned files but still errors come to change in other files..
>>
>> What to do?
>>
&g...
2018 Aug 02
2
Vectorizing remainder loop
Hi Hameeza,
Aside from Ashutosh's patch.....
When the vector width is that large, we can't keep vectorizing remainder like below. It'll be a huge code size if nothing else ---- hitting ITLB miss because of this is very bad, for example.
VF=2048 // main vector loop
VF=1024 // vectorized remaind...
2017 Aug 17
2
unable to emit vectorized code in LLVM IR
...8
#9 0x00007fcdebe2fa40 __libc_start_main
(/lib/x86_64-linux-gnu/libc.so.6+0x20a40)
#10 0x00000000007bc169 _start (/bin/lli+0x7bc169)
Stack dump:
0. Program arguments:lli sum-vec03.ll 5 2
Illegal instruction (core dumped)
What is wrong here? please help.
On Thu, Aug 17, 2017 at 11:51 PM, hameeza ahmed <hahmed2305 at gmail.com>
wrote:
> when i change it to following: then get error: remark: <unknown>:0:0: loop
> not vectorized: call instruction cannot be vectorized
> int main(int argc, char** argv) {
> int a[1000], b[1000], c[1000]; int g=0;
> for (int i=0; i<...
2017 Aug 17
4
unable to emit vectorized code in LLVM IR
...bb never
change this got further simplified to (aa+bb)*1000.
int main(int argc, char** argv) {
int a[1000], b[1000], c[1000]; int g=0;
int aa=atoi(argv[1]), bb=atoi(argv[2]);
for (int i=0; i<1000; i++) {
a[i]=aa, b[i]=bb;
c[i]=a[i] + b[i];
g+=c[i];
}
~Craig
On Thu, Aug 17, 2017 at 11:37 AM, hameeza ahmed <hahmed2305 at gmail.com>
wrote:
> why is it happening? is there any way to solve this?
>
> On Thu, Aug 17, 2017 at 10:09 PM, hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> even if i make my code as follows: vectorized instructions not get
>> emi...
2017 Oct 24
3
Jacobi 5 Point Stencil Code not Vectorizing
...is in the loop header, therefore cannot be if-converted
and is not a reduction. Polly also had difficulties with this
construction as well.
As presented at the dev meeting, VPlan will be able to insert a
shuffle instruction when encountering this situation.
Michael
2017-10-23 8:58 GMT+02:00 hameeza ahmed via llvm-dev <llvm-dev at lists.llvm.org>:
> stencil.ll is attached here.
>
> On Mon, Oct 23, 2017 at 11:37 AM, Serge Preis <spreis at yandex-team.ru> wrote:
>>
>>
>>
>> Hello,
>>
>> To me this is an issue in llvm loop vectorizer (if N...