search for: halid

>I think the real question is: Is this the best way to have a kind of 'halide buildbot' that can inform the LLVM developer community? Halide already has a buildbot running every few hours which is being used to inform LLVM developer community when something breaks. It would be a lot more useful however to have the tests in an LLVM repository to inform LLVM devs which t...

Some perhaps relevant aspects that make testing users of LLVM like Halide challenging: Halide uses the LLVM C++ APIs, but there isn't a good way to lock-step update it. So if we were to directly test Halide, it wouldn't link against the new LLVM. Practically speaking though, the LLVM IR generated by Halide should continue to work with newer LLVM optimizations...

...stable > > This involves extra work for everybody, but will help us all deliver higher-quality products. Plus, given the constant discussions about the difficulty for external projects to follow API updates, etc., this is a good way to help address those difficulties. > > The fact that Halide will provide extra coverage of our vector code generation (aside from whatever we happen to produce from our autovectorizers), and our JIT infrastructure, makes it a good candidate for this. Intel's ispc, POCL, (maybe whatever bit of Mesa uses LLVM), etc. would also be natural candidates shoul...

Hi all, TL;DR: Add *.bc to test-suite; llc *.bc; run some. We would like to propose adding bitcode tests to the llvm test-suite. Recent LLVM bugs [2-4] prompted us to look into upstreaming a subset of the tests the Halide library [1] is running and we'd like the community's feedback on moving forward with this. Halide uses LLVM and can generate bitcode, but we cannot add C++ tests to test-suite without including the library itself. This proposal is also potentially useful for other cases where there is no...

...xtra work for everybody, but will help us all deliver > higher-quality products. Plus, given the constant discussions about the > difficulty for external projects to follow API updates, etc., this is a > good way to help address those difficulties. > >> > >> The fact that Halide will provide extra coverage of our vector code > generation (aside from whatever we happen to produce from our > autovectorizers), and our JIT infrastructure, makes it a good candidate for > this. Intel's ispc, POCL, (maybe whatever bit of Mesa uses LLVM), etc. > would also be natu...

...t will help us all > deliver higher-quality products. Plus, given the constant > discussions about the difficulty for external projects to > follow API updates, etc., this is a good way to help address > those difficulties. > > The fact that Halide will provide extra coverage of our vector > code generation (aside from whatever we happen to produce from > our autovectorizers), and our JIT infrastructure, makes it a > good candidate for this. Intel's ispc, POCL, (maybe whatever > bit of Mesa use...

...:16 AM, Alina Sbirlea via llvm-dev <llvm-dev at lists.llvm.org> wrote: >>>>>> >>>>>> All, >>>>>> >>>>>> To get the discussion going in a focused manner, here is an initial patch with a running test. The test is from the Halide suite and is checking the correctness of several simd operations. >>>>>> (Notes: the patch is large due to the number of operations being tested; >>>>>> I expect a lot of changes before actually landing it, this is simply to continue the discussion using a conc...

...xtra work for everybody, but will help us all deliver > higher-quality products. Plus, given the constant discussions about the > difficulty for external projects to follow API updates, etc., this is a > good way to help address those difficulties. > >> > >> The fact that Halide will provide extra coverage of our vector code > generation (aside from whatever we happen to produce from our > autovectorizers), and our JIT infrastructure, makes it a good candidate for > this. Intel's ispc, POCL, (maybe whatever bit of Mesa uses LLVM), etc. > would also be natu...

...gt; > > On Feb 29, 2016, at 11:16 AM, Alina Sbirlea via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > All, > > To get the discussion going in a focused manner, here is an initial patch with a running test. The test is from the Halide suite and is checking the correctness of several simd operations. > (Notes: the patch is large due to the number of operations being tested; > I expect a lot of changes before actually landing it, this is simply to continue the discussion using a concrete example.) > http://reviews.llvm....

On Mon, Oct 10, 2016 at 1:14 PM, Renato Golin <renato.golin at linaro.org> wrote: > On 10 October 2016 at 19:39, Alina Sbirlea <alina.sbirlea at gmail.com> > wrote: > > Now, for ARM archs Halide is currently generating explicit VSTn > intrinsics, > > with some of the patterns I described, and I found no reason why Halide > > shouldn't generate a single shuffle, followed by a generic vector store > and > > rely on the interleaved access pass to generate the righ...

...wever, right now the tests are only running llc, so the optimization level is not that impactful and it is not clear to me that a miscompile would be detected this way. Which lead me to a separate question for Alina: is this IR "unoptimized"? What kind of optimization pipeline is used by Halide? Is the plan to only exercise the CodeGen? > > I think it pretty important to not phrase everything in terms of C or C++ or Clang... =/ > > What if there are IR constructs that simply cannot be produced by C++? We're adding lots of those for managed languages. Having a first-cl...

...gt; > > > > > > > > > > > > > > To get the discussion going in a focused manner, here is > > > > > > > an > > > > > > > initial > > > > > > > patch with a running test. The test is from the Halide > > > > > > > suite > > > > > > > and > > > > > > > is > > > > > > > checking the correctness of several simd operations. > > > > > > > > > > > > > > > > > >...

...On Feb 29, 2016, at 11:16 AM, Alina Sbirlea via llvm-dev < >>> llvm-dev at lists.llvm.org> wrote: >>> >>> All, >>> >>> To get the discussion going in a focused manner, here is an initial >>> patch with a running test. The test is from the Halide suite and is >>> checking the correctness of several simd operations. >>> (Notes: the patch is large due to the number of operations being tested; >>> I expect a lot of changes before actually landing it, this is simply to >>> continue the discussion using a con...

...uot;right" patterns, the pass is doing a good job for loads already) The examples you gave come mostly from loop vectorization, which, as I understand it, was the reason for adding the interleaved access pass. I'm looking at a different usecase. The code in question is generated by a DSL (Halide), and it's directly generating LLVM bitcode. The computations do come originally from loops, but they are pre-processed by Halide, followed by vector code generation as bitcode. The patters I'm targeting are not generated AFAIK from the loop vectorization or SLP passes. Now, for ARM archs...

...t;> >> >> On Feb 29, 2016, at 11:16 AM, Alina Sbirlea via llvm-dev < >> llvm-dev at lists.llvm.org> wrote: >> >> All, >> >> To get the discussion going in a focused manner, here is an initial patch >> with a running test. The test is from the Halide suite and is checking the >> correctness of several simd operations. >> (Notes: the patch is large due to the number of operations being tested; >> I expect a lot of changes before actually landing it, this is simply to >> continue the discussion using a concrete example.)...

...at 11:16 AM, Alina Sbirlea via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >>> >>> All, >>> >>> To get the discussion going in a focused manner, here is an initial patch with a running test. The test is from the Halide suite and is checking the correctness of several simd operations. >>> (Notes: the patch is large due to the number of operations being tested; >>> I expect a lot of changes before actually landing it, this is simply to continue the discussion using a concrete example.) >>&...

...Visual Studio 2015 (using CMake 3.2.1). ## Broken target properties in LLVMExports.cmake LLVM itself builds fine but when our project tries to do ``find_package(LLVM)`` we get the following error message (see [2] for context). ``` -- Looking for LLVM CMake Warning (dev) at C:/Users/me/Documents/halide/llvm-build/share/llvm/cmake/LLVMExports.cmake:232 (set_target_properties): Syntax error in cmake code at C:/Users/me/Documents/halide/llvm-build/share/llvm/cmake/LLVMExports.cmake:233 when parsing string LLVMObject;LLVMSupport;C:\Program Files (x86)\Microsoft Visual Studio 14.0\DIA...

Hi everyone, We are getting the following error when building the Halide library [1] (the component in question is GlobalISel) llvm-config: [...]/llvm/tools/llvm-config/llvm-config.cpp:86: void VisitComponent(const string&, const llvm::StringMap<AvailableComponent*>&, std::set<AvailableComponent*>&, std::vector<std::basic_string<char>...

...800, Ahmed Bougacha via llvm-dev wrote: > +Quentin > > > -Ahmed > > On Fri, Feb 12, 2016 at 10:16 AM, Alina Sbirlea via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > Hi everyone, > > > > We are getting the following error when building the Halide library [1] > > (the component in question is GlobalISel) > > > > llvm-config: [...]/llvm/tools/llvm-config/llvm-config.cpp:86: void VisitComponent(const string&, const llvm::StringMap<AvailableComponent*>&, std::set<AvailableComponent*>&, std::vector<s...

...On Feb 29, 2016, at 11:16 AM, Alina Sbirlea via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> All, >> >> To get the discussion going in a focused manner, here is an initial patch with a running test. The test is from the Halide suite and is checking the correctness of several simd operations. >> (Notes: the patch is large due to the number of operations being tested; >> I expect a lot of changes before actually landing it, this is simply to continue the discussion using a concrete example.) >> http://r...