Displaying 6 results from an estimated 6 matches for "gzz".
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2004 Dec 23
1
RV: As root and as any user
...root at server
?
and it?s just fine, even i can use CVS software, but if a try to use it
with other user it doesn`t work
?
$ ssh any at server
?
ask me for a password and it wrote me, ?have a lot of fun? and
inmediatly ?connection to server closed?
could you please help me.
?
?
Enrique Quintanilla Gzz.
Auto Summit Commercial Services, S.A. de C.V.
Tel. (81) 88 65 73 89
?
?
2018 Apr 11
5
RFC: Supporting the RISC-V vector extension in LLVM
...in the process of being updated.
I will also be at EuroLLVM with a lightning talk and poster on this
subject, so if you're there as well, we can discuss in person.
[1]
https://content.riscv.org/wp-content/uploads/2017/12/Wed-1330-RISCVRogerEspasaVEXT-v4.pdf
[2] https://www.youtube.com/watch?v=GzZ-8bHsD5s
[3] https://github.com/riscv/riscv-isa-manual/
# Summary
First-class support for the RISC-V vector ISA requires representing a
hardware vector length that is not just unknown at compile time, but also
changes during execution. This in turn places some restrictions on code
motion: the vec...
2018 Apr 12
0
RFC: Supporting the RISC-V vector extension in LLVM
...>
> I will also be at EuroLLVM with a lightning talk and poster on this
> subject, so if you're there as well, we can discuss in person.
>
> [1]
> https://content.riscv.org/wp-content/uploads/2017/12/Wed-1330-RISCVRogerEspasaVEXT-v4.pdf
> [2] https://www.youtube.com/watch?v=GzZ-8bHsD5s
> [3] https://github.com/riscv/riscv-isa-manual/
>
>
> # Summary
>
> First-class support for the RISC-V vector ISA requires representing a
> hardware vector length that is not just unknown at compile time, but also
> changes during execution. This in turn places some...
2018 Apr 13
0
RFC: Supporting the RISC-V vector extension in LLVM
...on.
>>
>> [1]
>> https://content.riscv.org/wp-content/uploads/2017/12/Wed-133
>> 0-RISCVRogerEspasaVEXT-v4.pdf <https://content.riscv.org/wp-
>> content/uploads/2017/12/Wed-1330-RISCVRogerEspasaVEXT-v4.pdf>
>> [2] https://www.youtube.com/watch?v=GzZ-8bHsD5s
>> [3] https://github.com/riscv/riscv-isa-manual/
>>
>>
>> # Summary
>>
>> First-class support for the RISC-V vector ISA requires representing a
>> hardware vector length that is not just unknown at compile time, but also
>> change...
2018 Apr 16
1
RFC: Supporting the RISC-V vector extension in LLVM
...so if you're there as well, we can discuss in person.
[1]
https://content.riscv.org/wp-content/uploads/2017/12/Wed-1330-RISCVRogerEspasaVEXT-v4.pdf <https://content.riscv.org/wp-content/uploads/2017/12/Wed-1330-RISCVRogerEspasaVEXT-v4.pdf>
[2] https://www.youtube.com/watch?v=GzZ-8bHsD5s
[3] https://github.com/riscv/riscv-isa-manual/
# Summary
First-class support for the RISC-V vector ISA requires representing a hardware vector length that is not just unknown at compile time, but also changes during execution. This in turn places some restrictions on code mot...
2009 Jul 23
1
[PATCH server] changes required for fedora rawhide inclusion.
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zNC8Nc9L_QyK!buFt9e3#(|mdqDXt!4XaqPDiT1|J!6tr&A7pYld!9P$edO;g1JJbw
z^luX(HD2PD>@x+7PadgzZ`g2n>uVcahKoYuN}wTJFse!5_bRUbTu8e<=_#W<rjleP
zArMx-zDS~5l*tMLNBU^CH{p;CrRzRw^_gb%IcnKDw*dgCIu^eo=f2Rjb<#LN6Pk-1
zgj>V1+36S;_dU)e)LF%^4oXI(g><}9yZnK}GWx>RijjuuP41@!fI2mn+s~JWxtrW7
z>oMLfi)7d+V?7>6F%YYT?a@^2 at u;=^oz0t}&%D3dJ^QEkUSYq9*m|#JRoZU4r#Z~=
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