search for: gv11b

From: Thierry Reding <treding at nvidia.com> Hi Ben, these are a couple of patches that are in preparation for adding GV11B support. The fundamental issue that these are trying to solve is that the GV11B is the first Tegra incarnation of the GPU where the aperture really matters. All prior generations would accept any of them. For dGPUs we usually allocate memory in VRAM, so the default aperture (0) is correct. However...

...gt; > Hi Ben, > > here's a revised subset of the patches I had sent out a couple of weeks > ago. I've reworked the BAR2 accesses in the way that you had suggested, > which at least for GP10B turned out to be fairly trivial to do. I have > not looked in detail at this for GV11B yet, but a cursory look showed > that BAR2 is accessed in more places, so the equivalent for GV11B might > be a bit more involved. > > Other than that, not a lot has changed since then. I've added a couple > of precursory patches to add IOMMU helper dummies for the case where &g...

...> > Hi Ben, > > here's a revised subset of the patches I had sent out a couple of weeks > ago. I've reworked the BAR2 accesses in the way that you had suggested, > which at least for GP10B turned out to be fairly trivial to do. I have > not looked in detail at this for GV11B yet, but a cursory look showed > that BAR2 is accessed in more places, so the equivalent for GV11B might > be a bit more involved. > > Other than that, not a lot has changed since then. I've added a couple > of precursory patches to add IOMMU helper dummies for the case where &gt...

From: Thierry Reding <treding at nvidia.com> The purpose of BAR1 is primarily to make memory accesses coherent. However, some GPUs do not have BAR1 functionality. For example, the GV11B found on the Xavier SoC is DMA coherent and therefore doesn't need BAR1. Implement a variant of FIFO channels that work without a mapping of instance memory through BAR1. XXX ensure memory barriers are in place for writes Signed-off-by: Thierry Reding <treding at nvidia.com> --- Hi Ben...

On Tue, 17 Sep 2019 at 01:18, Thierry Reding <thierry.reding at gmail.com> wrote: > > From: Thierry Reding <treding at nvidia.com> > > The gk20a (as well as all subsequent Tegra instantiations of the GPU) do > in fact use the same apertures as regular GPUs. Prior to gv11b there are > no checks in hardware for the aperture, so we get away with setting VRAM > as the aperture for buffers that are actually in system memory. Can GK20A take comptags with aperture set to system memory? For some reason I can recall, I was under the impression PTEs needed to be pointe...

...ing <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the equivalent for GV11B might be a bit more involved. Other than that, not a lot has changed since then. I've added a couple of precursory patches to add IOMMU helper dummies for the case where IOMMU is disabled (as sugge...

...ing <treding at nvidia.com> Hi Ben, here's a revised subset of the patches I had sent out a couple of weeks ago. I've reworked the BAR2 accesses in the way that you had suggested, which at least for GP10B turned out to be fairly trivial to do. I have not looked in detail at this for GV11B yet, but a cursory look showed that BAR2 is accessed in more places, so the equivalent for GV11B might be a bit more involved. Other than that, not a lot has changed since then. I've added a couple of precursory patches to add IOMMU helper dummies for the case where IOMMU is disabled (as sugge...

From: Thierry Reding <treding at nvidia.com> The gk20a (as well as all subsequent Tegra instantiations of the GPU) do in fact use the same apertures as regular GPUs. Prior to gv11b there are no checks in hardware for the aperture, so we get away with setting VRAM as the aperture for buffers that are actually in system memory. Signed-off-by: Thierry Reding <treding at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h | 1 - drivers/gpu/drm/nouveau/nvk...

...at 01:18, Thierry Reding <thierry.reding at gmail.com> wrote: > > > > From: Thierry Reding <treding at nvidia.com> > > > > The gk20a (as well as all subsequent Tegra instantiations of the GPU) do > > in fact use the same apertures as regular GPUs. Prior to gv11b there are > > no checks in hardware for the aperture, so we get away with setting VRAM > > as the aperture for buffers that are actually in system memory. > Can GK20A take comptags with aperture set to system memory? For some > reason I can recall, I was under the impression PTEs...

On Tue, 17 Sep 2019 at 01:04, Thierry Reding <thierry.reding at gmail.com> wrote: > > From: Thierry Reding <treding at nvidia.com> > > The GPUs found on Tegra SoCs have registers that can be used to read the > WPR configuration. Use these registers instead of reaching into the > memory controller's register space to read the same information. > >

...39;t actually test for the WPR size when it loads the firmware. I only ran into this when implementing the WPR info register readout because Nouveau would refuse to load the firmware because it didn't fit into what it thought was the WPR. Anyway, I've tested this on all of gm20b, gp10b and gv11b and the above computations give me the same values that the (SoC) firmware claims that it configured the WPR with. Given the above, do you see any further use for acr_r352_wpr_is_set()? Should I follow up with a patch removing it? Thierry > > > + > > + /* > > +...