search for: guest_paging_levels

Clearing out my local queue of changes before applying other''s.

...f(r->gpl2) != ri->extra_words * 4) { - fprintf(warn, "%s: expected %d bytes for %d-level guest, got %d!\n", + fprintf(warn, "%s: expected %zd bytes for %d-level guest, got %d!\n", __func__, sizeof(r->gpl2), h->v->guest_paging_levels, ri->extra_words * 4); dump_unexpected_and_exit(ri); @@ -5754,7 +5754,7 @@ case 3: if(sizeof(r->gpl3) != ri->extra_words * 4) { - fprintf(warn, "%s: expected %d bytes for %d-level guest, got %d!\n", +...

Hi, I just added 32GB memory in my system and wanted Xen to see that memory, so enabled PAE in xen0 and XenU. I did a make menuconfig in xen0 and xenU, then did a make in xen-unstable and a make install. Whilebooting this kernel, I get the above error PAE mode mismatch. I looked under xen/include/asm-x86/processor.h has #define X86_CR4_PAE defined and so does cpufeature.h have this defined.

...print of the shadow code and reduce pipeline flushes from mispredicted branches. To keep from having to maintain duplicate logic across 6 different bits of code, we use a single source code file, and compiler directives to specify mode-specific code. This file is shadow2.c, and is built once with GUEST_PAGING_LEVELS and SHADOW_PAGING_LEVELS set to the appropriate combination. The compiler is set to redefine the functions from sh2_[function_name]() to sh2_[function_name]__shadow_[m]_guest_[n] for n-on-m mode. At the end of shadow2.c is a structure containing function pointers for each of the mode-specifi...

We saw these issues in recent ChangeSet: 1. Reboot fail in Guest OS: Reboot in guest will close current qemu windows but does not create a new qemu window to restart 32bit HV/xen0: 2. 4 LTP math cases(float_bessel, float_exp_log, float_power and float_trigo) sometime fail. (775) 3. Kernel build in VMX may meet kernel panic. It complains like: "<0> Kernel panic - not syncing:

This patch series is a reworking of a series developed by Mukesh Rathor at Oracle. The entirety of the design and development was done by him; I have only reworked, reorganized, and simplified things in a way that I think makes more sense. The vast majority of the credit for this effort therefore goes to him. This version is labelled v13 because it is based on his most recent series, v11.

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):