search for: guarantees

Dear all, I''ve got a working HTB configuration with iptables, fwmark, SFQ etc. At the moment, I can mark traffic and give it a maximum bandwidth and a minimum guaranteed bandwidth, so far so good. What I would like to do is the following: In stead of defining a min/max for a certain type of traffic (e.g. http, ftp whatever), I would like to define a "minimum guaranteed bandwidth

Hi, can someone tell me whether applications can expect the write requests they make to be executed in order? For instance, suppose an application requests that a file be deleted, and then that another file be moved to an unrelated place. Will these events always happen in that order? Or to put it another way, if something unexpected happens in the meantime (say the computer crashes), is it

...be an issue Not having great experience with hosting providers, I''m not really sure how vendors such as Dreamhost would fit these requirements. How reliable are their backups? What security arrangements are there around online and backed up data ? What do they offer in terms of uptime guarantees? Do they provide failover hardware as part of their "regular" offerings, or is that available as an option? Do they have some sort of ISO or other accreditation saying that their processes are documented/reliable/...? I''ve tried to find this info at the Web sites of several co...

> Then why does the Release Note say > " the operation is guaranteed to not overflow". It means that the person who wrote the IR has guaranteed that there's no overflow (by some means) so LLVM can assume it during optimisation. This guarantee might come from doing explicit checks before executing the add/sub; or perhaps from performing the operation after a sext so that the

There is PostDominatorTree for determining post-dominance. Even if A post-dominates B and B is executed, that doesn't guarantee that A will be executed. For example, there could be an infinite loop in-between. Strong post-dominance makes the stronger guarantee that there will be no infinite loop from B to A. Do we have anything in LLVM for determining strong post-dominance and in general for

Hi, Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations. Instructions are defined as follow in TableGen: defm ADD64 : ALU32<"add", 1, 1, addc>; defm ADD64C : ALU32<"addrc", 1, 2, adde>; Let's assume that the carry bit is implicit and that the 2 operations must *always* be stuck together for the 64-bit add to

...ixing >> the ABI, provided that we document the attribute as such. It should >> be safe to use in compiler_rt once we modify its build system to use the >> just-built clang. > > I agree that we could certainly expose a calling convention with zero > binary-compatibility guarantees. I don't know if that would work for what > Richard wants, though. Notably, you can't stick that sort of thing in a > library that you haven't rev-locked to the compiler. CC'ing llvmdev. Okay, so per recent traffic on this thread, it sounds like this is not currently requi...

> On Apr 22, 2020, at 12:24 AM, Roman Lebedev via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On Wed, Apr 22, 2020 at 9:35 AM Adrien Guinet via llvm-dev > <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Hello everyone, >> >> After reading the nice blog post about _ExtInt, I was wondering whether >>

...acking storage. When migrating a domain, before the domain is started on the new host, you have to guarantee that all the domU vbd data is out of the block cache and written to the backing device. (In the case of a loopback device, whether this is sufficient depends on the cross-host coherency guarantees of the backing filesystem.) I cannot see that this takes place synchronously with the migration process. To me it looks like that the teardown/flush of the backing device depends on the action of the xenbus and the hotplug scripts and looks asynchronous to the migration process. So, am I right...

...nable the GuaranteedTailCall codegen option and obey a narrow set of rules, which includes always using fastcc. This is fairly awkward and doesn't solve my use case, since the ABI requires a particular convention. Instead, I propose that we add a new tail call marker, 'musttail', that guarantees that TCO will occur. I'm open to other naming suggestions. Some strawmen are 'tailonly' or 'guaranteedtail'. Along with it, I propose a set conservative of verifier enforced rules to follow to ensure that most reasonable backends will be able to perform TCO. It also ensures...

...BI, provided that we document the attribute as such. It should >>> be safe to use in compiler_rt once we modify its build system to use the >>> just-built clang. >> >> I agree that we could certainly expose a calling convention with zero >> binary-compatibility guarantees. I don't know if that would work for what >> Richard wants, though. Notably, you can't stick that sort of thing in a >> library that you haven't rev-locked to the compiler. > > CC'ing llvmdev. > > Okay, so per recent traffic on this thread, it sounds like...

Hello, Suppose I have x, which is a variable of class numeric. The calculations performed to yield x imply that mathematically it should be an integer , but due to round-off errors, it might not be (and so in either direction). The error is however small, so round(x) will yield the appropriate integer value. Moreover, this integer values is guaranteed to be representable by an

On Mon, Mar 21, 2016 at 4:42 PM, Rui Ueyama <ruiu at google.com> wrote: > On Tue, Mar 22, 2016 at 12:32 AM, David Blaikie <dblaikie at gmail.com> > wrote: > >> >> >> On Mon, Mar 21, 2016 at 4:21 PM, Rui Ueyama <ruiu at google.com> wrote: >> >>> From the user's point of view, I think it's still the same. As long as >>>

On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com> wrote: > Hi, > > Let's say we have a 32-bit architecture where 64-bit additions are done using 2 operations. > > Instructions are defined as follow in TableGen: > defm ADD64 : ALU32<"add", 1, 1, addc>; > defm ADD64C : ALU32<"addrc", 1, 2, adde>; > >

Suppose i write // foo.cpp __attribute__((section(“foo”))) int x; // bar.cpp __attribute__((section(“foo”))) int y; And i compile and link these two object files together using lld. What assumptions can I make regarding alignment/padding between the two symbols? I’m comfortable getting an answer by reading the source, but that won’t tell if any properties i discover are guaranteed or just

...n DI, see Felipe's answer. > Maybe I missed something. There seems to be no resolution to the problem. How can DA fix this without help from alias analysis? DependenceInfo is not using the AA interface correctly. Either DI has to be fixed, or another method added to AA that gives additional guarantees. Please see the bug report for details. > >> Since aliasPHI looks for any incoming value contradicting the NoAlias assumption, it would be equivalant to always return MayAlias. > I pasted the code snippet below with some extra comments. As far as the AA interface specification is con...

Hi ZFS Team, I have a couple of questions... Assume that the maximum slab size that ZFS supports is x. (I am assuming there is a maximum.) An application does a (single) write(2) for 2x bytes. Does ZFS/COW guarantee that either all the 2x bytes are persistent or none at all? Consider a case where there is a panic after x bytes has gone to disk and the change propagated to the uber block. Do

My hfsc rule .. tc qdisc add dev eth2 handle 1: root hfsc iptables -t mangle -N ms-all iptables -t mangle -N ms-all-chains iptables -t mangle -N ms-prerouting iptables -t mangle -A PREROUTING -j ms-prerouting iptables -t mangle -A ms-prerouting -j CONNMARK --restore-mark iptables -t mangle -A ms-prerouting -p udp --dport 4444 -j MARK --set-mark 1 iptables -t mangle -A ms-prerouting -p udp -m

Hi Francois, If you model the effect of your carry on the instructions, the scheduler (and the other backend passes) should ensure that nothing that affects the carry will be inserted between your two instructions (assuming they are issued with nothing affecting the carry in between in the first place). Therefore, you shouldn’t have to force them to be stuck together. If you still do, what Jakob

Hi Jakob, If glue operands are used by the scheduler to keep instructions together, why can't the register allocator also do this? Regards, Sam On 15/04/2013 23:12, Jakob Stoklund Olesen wrote: > On Apr 15, 2013, at 2:02 PM, Francois Pichet <pichet2000 at gmail.com> wrote: > >> Hi, >> >> Let's say we have a 32-bit architecture where 64-bit additions are