search for: gt2xx

Hi all, I just wanted to give a heads up to any NVIDIA users that NVIDIA are dropping support for older hardware based on G8xxx, G9xxx and GT2xx chipsets in their latest display drivers. The last version to support these older chipsets will be the current Long Lived 340.xx branch. If anyone is using NVIDIA driver packages from elrepo, legacy 340.xx driver packages are now available for those affected. There is a thread on the elrepo mailin...

...{ "GeForce 7", "G7x" }, { "GeForce 8", "G8x" }, - { "GeForce GTX 200", "NVA0" }, - { "GeForce GTX 400", "NVC0" }, + { "GeForce 9", "G9x" }, + { "GeForce GTX 2xx/3xx", "GT2xx" }, + { "GeForce GTX 4xx/5xx", "GFxxx" }, + { "GeForce GTX 6xx/7xx", "GKxxx" }, + { "GeForce GTX 9xx", "GMxxx" }, + { "GeForce GTX 10xx", "GPxxx" }, { NULL, NULL} }; -- 2.19.2

...addr /* >>> +*/ mov $r0 addr /* >> >> First of all, I know it is annoying, but we *need* to understand exactly >> what movw is now doing. >> >> Secondly, I seem to remember that a 32 bit mov was not added until fuc3 or > fuc5 Ah, right, fuc3 was on the GT2xx. Thanks! > >> something. Have you tried assembling this code on older fuc versions? Pretty >> sure it will fail. > That's what the imm32() macro is for. Right, with the mov replace with the imm32 macro, this patch will have my R-b!

...odifiers were not intended for use on desktop GPUs, and as a corollary, were not intended to support sharing block linear buffers across two different NVIDIA GPUs. v2: - Added canonicalize helper function v3: - Added additional bit to compression field to support Tesla (NV5x,G8x,G9x,GT1xx,GT2xx) class chips. Signed-off-by: James Jones <jajones at nvidia.com> --- include/uapi/drm/drm_fourcc.h | 122 +++++++++++++++++++++++++++++++--- 1 file changed, 114 insertions(+), 8 deletions(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3f987a.....

...(NV20) [ 304.159] GeForce 4Ti (NV25, NV28) [ 304.159] GeForce FX (NV3x) [ 304.159] GeForce 6 (NV4x) [ 304.159] GeForce 7 (G7x) [ 304.159] GeForce 8 (G8x) [ 304.159] GeForce 9 (G9x) [ 304.159] GeForce GTX 2xx/3xx (GT2xx) [ 304.159] GeForce GTX 4xx/5xx (GFxxx) [ 304.159] GeForce GTX 6xx/7xx (GKxxx) [ 304.159] GeForce GTX 9xx (GMxxx) [ 304.159] GeForce GTX 10xx (GPxxx) [ 304.159] (II) modesetting: Driver for Modesetting Kernel Drivers: kms [ 304.159] (II) [drm] nouveau interface version: 1.3.1...

...> + * starting with Fermi GPUs. Additionally, the mapping between page > + * kind and bit layout has changed at various points. > + * > + * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping > + * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping > + * 2 = Gob Height 8, Turing+ Page Kind mapping > + * 3 = Reserved for future use. > + * > + * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further > + * bit remapping step that occurs at an even low...

On 26/02/16 17:19, Karol Herbst wrote: > currently there is no change, because nobody uses those macros yet, but they > shouldn't stay broken > > Signed-off-by: Karol Herbst <nouveau at karolherbst.de> > --- > drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git

Beyond general review, I'm looking for feedback on a few things specifically here: -Is the level of backwards compatibility described here sufficient? Technically I can make the user space drivers support the old modifiers too, but that would mean the layout they specify would morph based on the GPU they're being used on, and sharing buffers between two different NV GPUs, which would

...Fermi GPUs. Additionally, the mapping between page > >> + * kind and bit layout has changed at various points. > >> + * > >> + * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping > >> + * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping > >> + * 2 = Gob Height 8, Turing+ Page Kind mapping > >> + * 3 = Reserved for future use. > >> + * > >> + * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further > >> + *...

Hi . I am having a very annoying problem not sure where the root of it lies When running FLdigi it runs fine for about 10 mineuts then i start getting errors leading to a complete lock up that needs a power button to free it up i get the following [ 653.080497] nouveau 0000:01:00.0: fifo: DMA_PUSHER - ch 3 [systemd-logind[462]] get 00000d3a24 [ 653.081461] nouveau 0000:01:00.0: gr:

On Wed, Jun 19, 2019 at 1:48 AM Sergey Senozhatsky <sergey.senozhatsky.work at gmail.com> wrote: > > On (06/19/19 01:20), Ilia Mirkin wrote: > > On Wed, Jun 19, 2019 at 1:08 AM Sergey Senozhatsky > > <sergey.senozhatsky.work at gmail.com> wrote: > > > > > > On (06/14/19 11:50), Sergey Senozhatsky wrote: > > > > dmesg > > > >

...e height of a GOB changed + * starting with Fermi GPUs. Additionally, the mapping between page + * kind and bit layout has changed at various points. + * + * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping + * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping + * 2 = Gob Height 8, Turing+ Page Kind mapping + * 3 = Reserved for future use. + * + * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further + * bit remapping step that occurs at an even lower level than the + *...

...e height of a GOB changed + * starting with Fermi GPUs. Additionally, the mapping between page + * kind and bit layout has changed at various points. + * + * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping + * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping + * 2 = Gob Height 8, Turing+ Page Kind mapping + * 3 = Reserved for future use. + * + * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further + * bit remapping step that occurs at an even lower level than the + *...

...starting with Fermi GPUs. Additionally, the mapping between page >> + * kind and bit layout has changed at various points. >> + * >> + * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping >> + * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping >> + * 2 = Gob Height 8, Turing+ Page Kind mapping >> + * 3 = Reserved for future use. >> + * >> + * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further >> + * bit remapping step that o...

http://bugs.freedesktop.org/show_bug.cgi?id=26980 Summary: GT230M/nouveau: X server hangs spontaneously Product: xorg Version: 7.5 Platform: x86-64 (AMD64) OS/Version: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau AssignedTo: nouveau at lists.freedesktop.org