Displaying 8 results from an estimated 8 matches for "gt215_ram_calc".
2016 Sep 21
8
[PATCH 0/5] GPU-DRM-nouveau: Fine-tuning for five function implementations
From: Markus Elfring <elfring at users.sourceforge.net>
Date: Wed, 21 Sep 2016 09:09:09 +0200
A few update suggestions were taken into account
from static source code analysis.
Markus Elfring (5):
Use kmalloc_array() in nvbios_iccsense_parse()
Use kmalloc_array() in gt215_link_train()
Delete unnecessary braces
Adjust a kzalloc() call in gt215_ram_new()
Add space after an
2016 Sep 21
0
[PATCH 3/5] GPU-DRM-nouveau: Delete unnecessary braces
...lc(u32 *vals, struct gt215_ltrain *train)
}
/* Find the best value for 0x1111e0 */
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++)
if (bins[i] > qty) {
bin = i + 3;
qty = bins[i];
}
- }
train->r_100720 = 0;
for (i = 0; i < 8; i++) {
@@ -729,9 +728,8 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq)
ram_mask(fuc, 0x1007e0, 0x22222222, r100760);
}
- if (device->chipset == 0xa3 && freq > 500000) {
+ if (device->chipset == 0xa3 && freq > 500000)
ram_mask(fuc, 0x100700, 0x00000006, 0x00000000);
- }
/* Final switch */
if (...
2018 Nov 05
1
[Bug 108658] New: gt215 scheduling while atomic warning
...e: events nvkm_pstate_work [nouveau]
Call trace:
dump_backtrace+0x0/0x1d0
show_stack+0x24/0x30
dump_stack+0x98/0xbc
__schedule_bug+0x64/0x80
__schedule+0x818/0x9b8
schedule+0x40/0xa8
gt215_pmu_send+0x274/0x2a8 [nouveau]
nvkm_pmu_send+0x60/0x80 [nouveau]
nvkm_memx_init+0x5c/0x120 [nouveau]
gt215_ram_calc+0x12f8/0x4d58 [nouveau]
gt215_ram_calc+0x2a0/0x4d58 [nouveau]
nvkm_pstate_work+0x18c/0x6b0 [nouveau]
process_one_work+0x1a8/0x438
worker_thread+0x54/0x3f8
kthread+0x104/0x130
ret_from_fork+0x10/0x18
[TTM] Zone kernel: Available graphics memory: 16460910 kiB
[TTM] Zone dma32: Available grap...
2015 Sep 29
10
All-round reclocking improvements
In bulletpoints:
- Add some support for G94 and G96 reclocking. Has been tested on literally
two cards, which is hardly adequate as "full coverage". On the other hand,
the changes were small enough to make me confident this might work for others
as well.
- Fix NV50 wait for VBLANK when no monitor is plugged in.
- Voltage related inprovements for GT21x.
- Slightly improve Keplers
2017 Apr 10
0
[PATCH 08/11] nvkm/ramgt215: Add train ptrn upload for GDDR5
...5_ram_train_fini(struct nvkm_ram *ram)
{
- if (ram->ltrain.mem)
- ram->base.func->put(&ram->base, &ram->ltrain.mem);
+ struct gt215_ram *gt215 = gt215_ram(ram);
+ if (gt215->ltrain.mem)
+ ram->func->put(ram, >215->ltrain.mem);
}
/*
@@ -554,7 +623,7 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq)
{
struct gt215_ram *ram = gt215_ram(base);
struct gt215_ramfuc *fuc = &ram->fuc;
- struct gt215_ltrain *train = &ram->ltrain;
+ struct gt215_ram_train_ddr3 *train = &ram->ltrain;
struct nvkm_subdev *subdev = &ram->base.fb->subde...
2015 May 22
11
Reclocking support for NVA0
Adds reclocking for NVA0, and a whole lot of work for other cards. Had these
patches collecting dust for a little, but tested them with both my NVA0,
and Martin's a while back. Success not guaranteed, but should be quite a
leap forward.
Happy reviewing and testing. Cheers,
Roy
2017 Apr 10
14
RESEND Preparations for Fermi DRAM clock changes
Two patches went missing as a result of PEBCAK. No v2 marks as nothing
changed really. Just resending for easier enforcement of patch order
in other people's trees. Sorry for the noise.
Original message:
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern
2017 Apr 10
11
Preparations for Fermi DRAM clock changes
No, no, these will not implement Fermi reclocking. This set of patches
contains some of the preparatory work that I deem stable enough to
move upstream. Notable changes
- Training pattern upload routines from GK104+ now shared with GT215+
- Timing calculation for Fermi
- GDDR5 MR calculation from VBIOS timing table v1.0. Also useful for that
pesky GT 240.
- A routine to translate a VBIOS init