Displaying 2 results from an estimated 2 matches for "gsub_0".
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ssub_0
2013 Apr 24
1
[LLVMdev] use of ARM GPRPair register class
...be used by instructions that do not return 64 bit value?
Example:
This is a simple example of machine instructions I caused to be generated. I
forced the LDRi12 instructions to use a GPRPair sub-register.
The copy into %vreg4 asserts because of the two definitions of vreg9,
coming from vreg9:gsub_0 and vreg9:gsub_1.
%vreg1<def> = COPY %R1; GPR:%vreg1
%vreg2<def> = MOVi32imm <ga:@a>; GPR:%vreg2
%vreg3<def> = ADDrsi %vreg2<kill>, %vreg1, 18, pred:14, pred:%noreg,
opt:%noreg; GPR:%vreg3,%vreg2,%vreg1
%vreg9:gsub_0<def,read-u...
2013 Jun 25
2
[LLVMdev] Adding a new ARM RegisterClass
I'm looking at an issue where we want a particular pseudo-instruction to
choose from a set of registers that is not included in the existing set of
RegisterClass definitions. More concretely, there is a RegisterClass in
ARMRegisterInfo.td defined as
def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
let