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stefan
2018 Apr 04
2
LLVM back end for the research Connex SIMD processor
...is designed to run efficiently BLAS routins, is an easily reconfigurable
low-power processor with scratchpad memory, a shift register for inter-lane communication,
a hardware sum-reduction tree and predictable performance - you can find details about it
at this address: http://users.dcae.pub.ro/~gstefan/2ndLevel/connex.html . The processor
has a clean design and its Verilog source code could be made open-source.
You can find the source code of the latest version of the compiler (LLVM back end and
extensions for Connex in the LoopVectorize module, etc) and runtime I develop for the
Connex...