Displaying 1 result from an estimated 1 matches for "grregsadditional".
2015 Nov 25
2
need help for customized backend LowerFormalArguments
...2], 32,
(add P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14,
P15)>;
// this is general purpose register class
def GRRegs : RegisterClass<"FOO", [i32], 32,
(add R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10)>;
// this is also general purpose register class
def GRRegsAdditional : RegisterClass<"FOO", [i32], 32,
(add R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14,
R15, SP)>;
If I have a piece of bitcode looks like this:
define i32 @_Z3fooii(i32 %a, i32 %b) #0 {
%1 = add nsw i32 %a, %b
ret i32 %1
}
I want the assembly looks like thi...