search for: grregs

...r, align 4 %0 = load i32* %n.addr, align 4 %sub = sub nsw i32 %0, 1 ret i32 %sub } But finally in code generation i am getting: ldc r2, #-1 add r0, r2, r0 Should this not be doing: ldc r2 #1 sub r0 r2 r0 I have defined both my add and sub instructions: def ADD : ALUInst<0b0001, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), "add $src1, $src2, $dst", [(set i32:$dst, (add i32:$src1, i32:$src2))]>; def SUB : ALUInst<0b0010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),...

...e offset is scaled by the size of the load or store. For example the load word instruction LDW takes an offset which is multiplied by 4 and added to the base pointer. This is dealt with in the patterns defined in XCoreInstrInfo.td. The following pattern is used for LDW: def : Pat<(load (add GRRegs:$addr, immUs4:$offset)), (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; immUs4 is true when offset is a multiple of 4 and the offset divided by 4 fits in an immediate. The div4_xform xform divides a constant by 4. These are both defined in XCoreInstrInfo.td. It sounds like...

Hi, my target architecture has a kind of "16bit addressing mode", i.e. one address does not address 8 bit but a 16bit chunk. Consequently, every constant used to calculate effective addresses must be divided by two. So far this is not such a problem for stack objects since FrameIndexes, function arguments etc. have a lot of custom lowering code where this can be done. But when it comes

...***************************************************************************************** In InstroInfo.td, I define a pseudo instruction like this : ****************************************************************************************** *let isPseudo = 1 in {* * def FOO : MyPseudoInst<(outs GRRegs:$dst) , (ins GRRegs:$src1, GRRegs:$src2),* * "foo $dst, $src1, $src2",* * [(set i32:$dst, (int_foo i32:$src1, i32:$src2))]> {* * }* *} * ******************************************************************************************** I want to ch...

Hi, I'm doing a backend port and I'm having trouble with adds that have negative immediates. My architecture only has instructions for subtracting and adding 8bit immediate values (they will be zero-extended, thus unsigned). Bigger immediates have to be moved in a register first. The problem is: Expressions like "b - 1" result in "add nsw i32 %b, -1" in LLVM IR. They

...ter. For example, in RegisterInfo.td , I have following register classes: // this is for storing parameters only def PRegs : RegisterClass<"FOO", [i32], 32, (add P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15)>; // this is general purpose register class def GRRegs : RegisterClass<"FOO", [i32], 32, (add R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10)>; // this is also general purpose register class def GRRegsAdditional : RegisterClass<"FOO", [i32], 32, (add R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, SP...

Hi, All, I want to add one intrinsic function for my particular backend. Let's say the intrinsic function is named "foo" which takes two i32 inputs and has one i32 output. First, I add this line "def int_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadArgMem]>;" in /include/llvm/IR/Intrinsics.td. Then, in my target/InstrInfo.td, I'm supposed

...size of > the load or store. For example the load word instruction LDW takes an > offset which is multiplied by 4 and added to the base pointer. This is > dealt with in the patterns defined in XCoreInstrInfo.td. The following > pattern is used for LDW: > > def : Pat<(load (add GRRegs:$addr, immUs4:$offset)), > (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; > Richard, thanks for your suggestion. However, I think what you describe is what I meant by 'only catch the targeted addresses of loads/stores', i.e. the address the instruction is readin...