Displaying 3 results from an estimated 3 matches for "gr8regclass".
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gpr8regclass
2013 Jan 18
0
[LLVMdev] llvm backend porting question ,
...d(MachinePointerInfo::getFixedStack(MVT::i8),
MachineMemOperand::MOStore,
MFI.getObjectSize(MVT::i8),
Align);
BuildMI(MBB, MI, DL, get(Picoblaze::STORETOSTACK ));//.addMemOperand(MMO);
if (RC == &Picoblaze::GR8RegClass)
{
// BuildMI(MBB, MI, DL, get(Picoblaze::ADD8ri ))
// .addReg(Picoblaze::BP)
// .addImm(FrameIdx);
BuildMI(MBB, MI, DL, get(Picoblaze::STORE_I))
.addImm(FrameIdx)
.addReg(SrcReg,getKillRegState(isKill))
;
// .addMemOperand(MMO); ;//addReg(Picoblaze::BP);
/...
2012 Apr 22
0
[LLVMdev] FYI: Removal of XXXRegisterClass from GenRegisterInfo.inc
...ind this is setting up register
classes in TargetLowering. For example,
addRegisterClass(MVT::i8, X86::GR8RegisterClass);
addRegisterClass(MVT::i16, X86::GR16RegisterClass);
addRegisterClass(MVT::i32, X86::GR32RegisterClass);
These should be changed to
addRegisterClass(MVT::i8, &X86::GR8RegClass);
addRegisterClass(MVT::i16, &X86::GR16RegClass);
addRegisterClass(MVT::i32, &X86::GR32RegClass);
Hopefully, this change won't cause too much trouble.
--
~Craig
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2007 Jul 03
2
[LLVMdev] Swaps of FP registers
...lock::iterator mi,
unsigned r1,
unsigned r2,
const TargetRegisterClass *rc
) const {
unsigned Opc;
if (rc == &X86::GR32RegClass) {
Opc = X86::XCHG32rr;
} else if (rc == &X86::GR16RegClass) {
Opc = X86::XCHG16rr;
} else if (rc == &X86::GR8RegClass) {
Opc = X86::XCHG8rr;
} else {
assert(0 && "Unknown regclass in add swap");
abort();
}
BuildMI(mbb, mi, Opc, 1, r1).addReg(r2);
}
thanks,
Fernando