Displaying 3 results from an estimated 3 matches for "gr64_tcw64".
2017 Aug 12
3
Mischeduler: Unknown reason for peak register pressure increase
I am working on a project where we are integrating an existing pre-RA scheduler into LLVM and we are trying to match our peak register pressure values with the machine instruction schedulers values while using X86. I am finding some mismatches in test cases like the one attached. The registers "AH" and "AL" are live-out but not live-in and I don't see that they are defined
2017 Jul 28
3
Purpose of various register classes in X86 target
...airly
straightforward(at least commands used in X86 td file). However, some of
the comments about the classes didn't fully make sense: I suppose the
constraints are probably derived from the X86 assembly language and I
should look there? In addition, some classes don't have any comments(eg:
GR64_TCW64) and I couldn't find much info elsewhere.
Also, I don't know how the TableGen'erated classes are derived. Would
reading TableGen's code help understand why those were generated and what
constraints they encode? Or should I take another approach?
-------------- next part -----------...
2017 Jul 27
2
Purpose of various register classes in X86 target
Hello everyone,
I noticed that there are several register classes defined in X86 target and
many of them are overlapping. Is there a list of all X86 register classes
documented somewhere? I found many listed in
X86GenRegisterInfo.inc(generated by tablegen) but unsure if that is the
complete list. Also, is there documentation on the role and purpose of
these classes and how the X86 backend decides