Displaying 10 results from an estimated 10 matches for "gr32regclass".
2013 Aug 05
0
[LLVMdev] Promote MVT::f32 load/store to MVT::i32 cause infinite loop in LegalizeDAG?
...AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
> >
> > Now SelectionDAGLegalize::LegalizeDAG() get stuck into an infinite loop.
> > What is going on?
> >
> > I still have the following:(but I think that's fine)
> > addRegisterClass(MVT::f32, &Opus::GR32RegClass);
>
> Have you specified a register class for MVT::i32? If not, I think that
> may be your problem.
>
> -Tom
>
Yes I have, f32 and i32 map to the same register class:
addRegisterClass(MVT::i32, &Opus::GR32RegClass);
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2013 Aug 05
2
[LLVMdev] Promote MVT::f32 load/store to MVT::i32 cause infinite loop in LegalizeDAG?
...i32);
setOperationAction(ISD::LOAD, MVT::f32, Promote);
AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
Now SelectionDAGLegalize::LegalizeDAG() get stuck into an infinite loop.
What is going on?
I still have the following:(but I think that's fine)
addRegisterClass(MVT::f32, &Opus::GR32RegClass);
Thanks.
(My LLVM is ~3 months old)
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2013 Aug 05
1
[LLVMdev] Promote MVT::f32 load/store to MVT::i32 cause infinite loop in LegalizeDAG?
...D, MVT::f32, Promote);
> AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
>
> Now SelectionDAGLegalize::LegalizeDAG() get stuck into an infinite loop.
> What is going on?
>
> I still have the following:(but I think that's fine)
> addRegisterClass(MVT::f32, &Opus::GR32RegClass);
Have you specified a register class for MVT::i32? If not, I think that
may be your problem.
-Tom
2012 Apr 22
0
[LLVMdev] FYI: Removal of XXXRegisterClass from GenRegisterInfo.inc
...R8RegisterClass);
addRegisterClass(MVT::i16, X86::GR16RegisterClass);
addRegisterClass(MVT::i32, X86::GR32RegisterClass);
These should be changed to
addRegisterClass(MVT::i8, &X86::GR8RegClass);
addRegisterClass(MVT::i16, &X86::GR16RegClass);
addRegisterClass(MVT::i32, &X86::GR32RegClass);
Hopefully, this change won't cause too much trouble.
--
~Craig
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2007 Jul 03
2
[LLVMdev] Swaps of FP registers
...instruction for floating point?
My function to insert swaps is like:
void X86RegisterInfo::swapRegs(
MachineBasicBlock & mbb,
MachineBasicBlock::iterator mi,
unsigned r1,
unsigned r2,
const TargetRegisterClass *rc
) const {
unsigned Opc;
if (rc == &X86::GR32RegClass) {
Opc = X86::XCHG32rr;
} else if (rc == &X86::GR16RegClass) {
Opc = X86::XCHG16rr;
} else if (rc == &X86::GR8RegClass) {
Opc = X86::XCHG8rr;
} else {
assert(0 && "Unknown regclass in add swap");
abort();
}...
2014 Feb 08
2
[LLVMdev] selecting ISD node - help
...the DAG looks like how I think it supposed
to look like (attached the picture below).
if(Subtarget->is64Bit())
{
idReg = X86::RCX;
resultReg = MF.addLiveIn(X86::RAX, &X86::GR64RegClass);
}
else
{
idReg = X86::ECX;
resultReg = MF.addLiveIn(X86::EAX, &X86::GR32RegClass);
}
idRegValue = CurDAG->getRegister(idReg, resultType);
SDValue setIdNode = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
idRegValue, id, SDValue());
SDValue rdmsrNode = SDValue(CurDAG->getMachineNode(X86::RDMSR, dl,
MVT::Glue, setIdNode.getValue(1)), 0);
SDValue re...
2011 Mar 31
2
[LLVMdev] Unallocated address error triggered from ::RALinScan::assignRegOrStackSlotAtInterval on i386
.../usr/local/gcc/4.5.2/lib/gcc/i686-pc-linux-gnu/4.5.2/../../../../include/c++/4.5.2/bits/stl_tree.h:1449
#14 0x00b52b58 in (anonymous namespace)::RALinScan::assignRegOrStackSlotAtInterval(llvm::LiveInterval*) ()
from /usr/local/llvm/svn-r128446/lib/libLLVM-3.0svn.so
#15 0x0169dc00 in llvm::X86::GR32RegClass () from /usr/local/llvm/svn-r128446/lib/libLLVM-3.0svn.so
Problem occurs when I am attempting to run a large module in JIT, from
ExecutionEngine::runFunction, after static constructors have succeeded.
EngineKind=1, OptLevel=3. When I change OptLevel to 0 problem disappears.
llvm::NoFramePointerE...
2014 Feb 08
2
[LLVMdev] selecting ISD node - help
Hey, I wanted to add an intrinsics to read MSRs.
So I added the intrinsics and lowered it to a new ISD node I created
ISD::RDMSR, its first operand is the MSR id.
I added a case in X86DAGToDAGISel::Select for ISD::RDMSR.
Now I know rdmsr works like so:
mov r/ecx, <id>
rdmsr
r/eax holds the lower 32/64 bit
>From what I understood this needs a Token Factor node, nodes which are
2008 Apr 16
0
[LLVMdev] Being able to know the jitted code-size before emitting
..."llvm/Support/CommandLine.h"
> +#include "llvm/Support/Debug.h"
> #include "llvm/Target/TargetOptions.h"
> +#include "llvm/Target/TargetAsmInfo.h"
>
> using namespace llvm;
>
> @@ -2263,3 +2265,556 @@
> else
> return &X86::GR32RegClass;
> }
> +
> +unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
> + switch (Desc->TSFlags & X86II::ImmMask) {
> + case X86II::Imm8: return 1;
> + case X86II::Imm16: return 2;
> + case X86II::Imm32: return 4;
> + case X86II::Imm64: return 8;
>...
2008 Apr 15
4
[LLVMdev] Being able to know the jitted code-size before emitting
OK, here's a new patch that adds the infrastructure and the
implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize.
Both functions are virtual functions defined in TargetInstrInfo.h.
For X86, I moved some commodity functions from X86CodeEmitter to
X86InstrInfo.
What do you think?
Nicolas
Evan Cheng wrote:
>
> I think both of these belong to TargetInstrInfo. And