search for: gr32_tc

...o GHC's cc 10. > | In detail: > | * Inserted new symbol "cc 11" (CallingConv::HiPE). > | * Created cc and retcc for both 32 and 64 bit. > | * HiPE cc defines no calleE-save registers. > | * HiPE cc supports tail call optimization. > > 0002: > | Hack fix for GR32_TC registers. > | Add EBX, EDI to GR32_TC register class to handle a "ran out of registers during > | register allocation" in case of tailcall existance because in EAX, ECX, EDX > | are all argument registers in HiPE CC.

...g convention (cc 11) for HiPE similar to GHC's cc 10. | In detail: | * Inserted new symbol "cc 11" (CallingConv::HiPE). | * Created cc and retcc for both 32 and 64 bit. | * HiPE cc defines no calleE-save registers. | * HiPE cc supports tail call optimization. 0002: | Hack fix for GR32_TC registers. | Add EBX, EDI to GR32_TC register class to handle a "ran out of registers during | register allocation" in case of tailcall existance because in EAX, ECX, EDX | are all argument registers in HiPE CC. Regards, Yiannis On Tue, Apr 24, 2012 at 04:29:38PM +0300, Yiannis Tsiour...

...o GHC's cc 10. > | In detail: > | * Inserted new symbol "cc 11" (CallingConv::HiPE). > | * Created cc and retcc for both 32 and 64 bit. > | * HiPE cc defines no calleE-save registers. > | * HiPE cc supports tail call optimization. > > 0002: > | Hack fix for GR32_TC registers. > | Add EBX, EDI to GR32_TC register class to handle a "ran out of registers during > | register allocation" in case of tailcall existance because in EAX, ECX, EDX > | are all argument registers in HiPE CC. _______________________________________________ LLVM Develope...

Hi, Following Chris' advice, I will rebase the patches and break them in 3 distinct emails (one at a time) in order to be easier for a reviewer to approve/comments. Please note that the three patches while being code-wise independent, they 're strongly-connected *semantically*, meaning that including just a subset of these patches to LLVM's code base is quite weak if the others are

Hi, We 've been working on an LLVM backend for High Performance Erlang (HiPE) [1], the native code compiler of Erlang/OTP [2]. ErLLVM [3] targets the X86 and AMD64 architectures for now but there is some ongoing work from a team on the Uppsala University to also support ARM. In our implementation, we have paid special attention on retaining ABI-compatibility with the Erlang Runtime System in

I am working on a project where we are integrating an existing pre-RA scheduler into LLVM and we are trying to match our peak register pressure values with the machine instruction schedulers values while using X86. I am finding some mismatches in test cases like the one attached. The registers "AH" and "AL" are live-out but not live-in and I don't see that they are defined